1、Embedded System Architecture Design-Timing and AddersJun WANG1OutlineTimingCritical pathGlitchAdderHFAFARCACLA2Delay between input change and output changingHow to build fast circuits?Timing3 Critical (Long) Path: tpd = 2tpd_AND + tpd_OR Short Path: tcd = tcd_ANDCritical (Long) & Short Paths4When a

2、single input change causes multiple output changesGlitches5What happens when A = 0, C = 1, B falls?Glitch Example6Glitch Example (cont.)7Fixing the Glitch8Glitches dont cause problems because of synchronous design conventions (see Chapter 3)Its important to recognize a glitch: in simulations or on o

3、scilloscopeCant get rid of all glitches simultaneous transitions on multiple inputs can also cause glitchesWhy Understand Glitches?91-Bit Adders10LabsLab 2ComparatorLab 3 4-bits Mux1-Bit Adders121-Bit Adders13Chain 1-bit adders togetherCarry ripples through entire chainDisadvantage: slowRipple-Carry

4、 Adder14tripple = NtFA where tFA is the delay of a full adderIs it too LONG？Ripple-Carry Adder Delay15verilog1 bit FA （ with RTL description ）module FA( input a, b, cin output cout, sum ); / HDL modeling of 1 bit / full adder functionality 。/ complete themendmodule4 bit FA （ with structural descript

5、ion ）module adder( input3:0 A, B, output cout, output3:0 S ); wirec0, c1, c2; FA fa0(A0, B0, 1b0, c0, S0 ); FA fa1( . ); /complete themFA fa2( . ); FA fa3( . );endmoduleHow is behavioral description?16SchematicSchematicCritical path17Ripple-carry (RCA)(slow)Carry-lookahead (CLA)(fast)Study for your

6、homework MUST DO, as you will use it in lab session next weekCarry-lookahead adder faster for large adders but require more hardware Types of Adders 18Compute carry out (Cout) for k-bit blocks using generate and propagate signalsSome definitions:Column i produces a carry out by either generating a c

7、arry out or propagating a carry in to the carry outGenerate (Gi) and propagate (Pi) signals for each column:Column i will generate a carry out if Ai AND Bi are both 1. Gi = Ai BiColumn i will propagate a carry in to the carry out if Ai OR Bi is 1.Pi = Ai + BiThe carry out of column i (Ci) is: Ci = A

8、i Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1Carry-Lookahead Adder19Step 1: Compute Gi and Pi for all columns Step 2: Compute G and P for k-bit blocksStep 3: Cin propagates through each k-bit propagate/generate blockCarry-Lookahead Addition20Example: 4-bit blocks (G3:0 and P3:0) : G3:0 = G3 + P3 (G2 + P2 (G1

9、 + P1G0 ) P3:0 = P3P2 P1P0C3 = G3:0 + P3:0 C-1Generally, Gi:j = Gi + Pi (Gi-1 + Pi-1 (Gi-2 + Pi-2Gj ) Pi:j = PiPi-1 Pi-2PjCi = Gi:j + Pi:j Cj-1Carry-Lookahead Adder2132-bit CLA with 4-bit Blocks22SummaryAlways/Initial () vs assignProcedural assignment vs continuous assignment wire vs regwire used only in assign, synthesized as combinational circuit (net)reg used only in always, synthesized as combinational circuit (net), in (a or b)Sequential circuit (register), in (clk) = vs =Block assignment vs No-block assig