VHDLSimulation&SynthesisVHDLSimulation&Synthesis1BalanceofSignalDelayBalanceofSignalDelay2OptimizeofLateArrivedSignalLateArrivedSignalLateArrivedSignalOptimizeofLateArrivedSigna3Multiple‘IF’StatementMultiple‘IF’Statement4LateArrivedSignalLateArrivedSignal5LateArrivedSignal(Improvement)所有能選通b的控制信號組合LateArrivedSignal(Improveme6PriorityEncoded‘IF’ForLateArrivedSignalsEscapefromprevious2‘if’,butshouldbecaughtby‘z=b’selectionEndif;PriorityEncoded‘IF’ForLate7PriorityEncoded‘IF’ForLateArrivedControlSignalPriorityEncoded‘IF’ForLate8LateArrivedControlSignalA(1)A(2)A(3)A(4)A(5)A(6)zC(1)C(2)C(3)C(4)C(5)LateArrivedControlSignalA(19LateArrivedControlSignal(Improvement)A(1)A(2)A(3)A(4)A(5)A(6)z1C(1)C(2)C(3)C(5)C(4)A(4)z1zLateArrivedControlSignal(I10ImprovedCodeImprovedCode11LateArrivedSignalin‘CASE’Statement(contd.)LateArrivedSignalin‘CASE’12ImprovedCode(Schematic)ImprovedCode(Schematic)13VHDLCodeBeforeOptimize

(Case-WhenClasue)VHDLCodeBeforeOptimize

(Cas14VHDLCodeAfterOptimize

(Case-WhenClasue)MergeboththeCconditionandtheselconditionVHDLCodeAfterOptimize

(Case15Delayin‘CASE’Statement(Schematic)Sel(0)Sel(1)Sel(2)ZDelayin‘CASE’Statement(Sch16Delayin‘CASE’Statement(Improvement)Sel(0)0Sel(2)1Sel(1)Z1Z2ZDelayin‘CASE’Statement(Imp17Delayin‘CASE’StatementSel(1)isslowSel(1)=1Sel(1)=0Delayin‘CASE’StatementSel(118ImprovedCodeClosetofinaloutputImprovedCodeClosetofinalou19LongCalculationPathLongCalculationPath20LongCalculationPath(Schematic)LongCalculationPath(Schemat21ImprovedCodeImprovedCode22ImprovedCode(Schematic)ImprovedCode(Schematic)23DecoderUsingIndexingIn1_intasindexDecoderUsingIndexingIn1_int24Iisindex,in1_intiscomparedinloop.Out1(i)isaccessedbyvariableiDecoderUsingLoopIisindex,in1_intiscompare25DecoderUsingIndexingvs.‘Loop’DecoderUsingIndexingvs.‘Lo26MultipleInputsXORGateMultipleInputsXORGate27XORChains(Schematic)XORChains(Schematic)28XORTreeXORTree29XORTree(Schematic)XORTree(Schematic)30MultiplexChainMultiplexChain31MultiplexChain(Schematic)MultiplexChain(Schematic)32MultiplexTreeMultiplexTree33OperatorinConditionalExpressionOperatorinConditionalExpres34SchematicSchematic35ImprovedCodeImprovedCode36ImprovedCode(Schematic)ImprovedCode(Schematic)37UnintentionalLatchData_inData_outCond_1UnintentionalLatchData_inDa38UnnecessaryCalculationin‘LOOP’UnnecessaryCalculationin‘LO39CodingStyleForSynthesis(1)Omit waitforXXns;Omit (Q<=0afterXXns)UsingshifterregisterinsteadDQDQDQCodingStyleForSynthesis(1)40CodingStyleForSynthesis(2)OmitInitialValues

variableSUM:INTEGER:=0;Usingpoweronset/resetsignalinsteadDQRSCodingStyleForSynthesis(2)41CodingStyleForSynthesis(3)DonotusevariablesforconstantsUseconstCodingStyleForSynthesis(3)42CodingStyleForSynthesis(4)IndentingYourCodesCodingStyleForSynthesis(4)43CodingStyleForSynthesis(5)Usestd_logic9valueAutomaticallyinitializedtoanunknownvalueEasytoperformaboard-levelsimulationCodingStyleForSynthesis(5)44CodingStyleForSynthesis(6)DonotusebuffersCodingStyleForSynthesis(6)45VHDLSimulation&SynthesisVHDLSimulation&Synthesis46BalanceofSignalDelayBalanceofSignalDelay47OptimizeofLateArrivedSignalLateArrivedSignalLateArrivedSignalOptimizeofLateArrivedSigna48Multiple‘IF’StatementMultiple‘IF’Statement49LateArrivedSignalLateArrivedSignal50LateArrivedSignal(Improvement)所有能選通b的控制信號組合LateArrivedSignal(Improveme51PriorityEncoded‘IF’ForLateArrivedSignalsEscapefromprevious2‘if’,butshouldbecaughtby‘z=b’selectionEndif;PriorityEncoded‘IF’ForLate52PriorityEncoded‘IF’ForLateArrivedControlSignalPriorityEncoded‘IF’ForLate53LateArrivedControlSignalA(1)A(2)A(3)A(4)A(5)A(6)zC(1)C(2)C(3)C(4)C(5)LateArrivedControlSignalA(154LateArrivedControlSignal(Improvement)A(1)A(2)A(3)A(4)A(5)A(6)z1C(1)C(2)C(3)C(5)C(4)A(4)z1zLateArrivedControlSignal(I55ImprovedCodeImprovedCode56LateArrivedSignalin‘CASE’Statement(contd.)LateArrivedSignalin‘CASE’57ImprovedCode(Schematic)ImprovedCode(Schematic)58VHDLCodeBeforeOptimize

(Case-WhenClasue)VHDLCodeBeforeOptimize

(Cas59VHDLCodeAfterOptimize

(Case-WhenClasue)MergeboththeCconditionandtheselconditionVHDLCodeAfterOptimize

(Case60Delayin‘CASE’Statement(Schematic)Sel(0)Sel(1)Sel(2)ZDelayin‘CASE’Statement(Sch61Delayin‘CASE’Statement(Improvement)Sel(0)0Sel(2)1Sel(1)Z1Z2ZDelayin‘CASE’Statement(Imp62Delayin‘CASE’StatementSel(1)isslowSel(1)=1Sel(1)=0Delayin‘CASE’StatementSel(163ImprovedCodeClosetofinaloutputImprovedCodeClosetofinalou64LongCalculationPathLongCalculationPath65LongCalculationPath(Schematic)LongCalculationPath(Schemat66ImprovedCodeImprovedCode67ImprovedCode(Schematic)ImprovedCode(Schematic)68DecoderUsingIndexingIn1_intasindexDecoderUsingIndexingIn1_int69Iisindex,in1_intiscomparedinloop.Out1(i)isaccessedbyvariableiDecoderUsingLoopIisindex,in1_intiscompare70DecoderUsingIndexingvs.‘Loop’DecoderUsingIndexingvs.‘Lo71MultipleInputsXORGateMultipleInputsXORGate72XORChains(Schematic)XORChains(Schematic)73XORTreeXORTree74XORTree(Schematic)XORTree(Schematic)75MultiplexChainMultiplexChain76MultiplexChain(Schematic)MultiplexChain(Schematic)77MultiplexTreeMultiplexTree78OperatorinConditionalExpressionOperatorinConditionalExpres79SchematicSchematic80ImprovedCodeImprovedCode81ImprovedCode(Schematic)ImprovedCode(Schematic)82UnintentionalLatchData_inData_outCond_1UnintentionalLatchData_inDa83UnnecessaryCalculationin‘LOOP’UnnecessaryCalculationin‘LO84CodingStyleForSynthesis(1)Omit waitforXXns;Omit (Q<=0afterXXn