1、1. Shown below are buffer-chain designs. (1) Calculate the minimum delay of a chain of inverters for the overall effective fan-out of 64/1. (2) Using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply, design a circuit simulation scheme to verify them with their correspondent para

2、meters of N, f, and tp.(1) =1 F=64f=NF=3.6 N=3.246所以最佳反相器數目約為3通過仿真可以得到tphl=1.3568E-11 tplh=1.7498E-11 tp0=1.5533E-11(2)N=1時，tphl= 5.2735E-10 tplh= 8.1605E-10 tpd= 6.7170E-10N=2時，tplh=2.2478E-10 tphl=2.5567E-10 tpd=2.4023E-10N=3時，tphl=2.0574E-10 tplh=2.1781E-10 tpd=2.1178E-10N=4時，tplh=2.1579E-10 tphl

3、=2.2189E-10 tpd=2.1884E-10從仿真結果可以看出N=3或者N=4時延遲時間最優，且N=2、3、4得到的仿真延遲時間與理論推導的時間比較接近，比例基本上是18、15、15.3，而N=1時仿真得到的延遲時間遠小于理論推導的時間，但是最優結果依舊是N=3,f=4,tp=15。* SPICE INPUT FILE: Bsim3demo1.sp-a chain of inverters.param Supply=1.8.lib'C:synopsysHspice_A-2007.09tsmc018mm018.l' TT.option captab.option list

4、 node post measout.tran 10p 6000p*.param tdval=10p.meas tran tplh trig v(in) val=0.9 td=tdval rise=2+targ v(out) val=0.9 rise=2.meas tran tphl trig v(in) val=0.9 td=tdval fall=2+targ v(out) val=0.9 fall=2.meas tpd param='(tphl+tplh)/2'*macro definitions*nmos1*.subckt nmos1 n1 n2 n3mn n1 n2 n

5、3 Gnd nch l=0.2u w=0.4u ad=0.2p2 pd=0.4u as=0.2p2 ps=0.4u.ends nmos1*pmos1*.subckt pmos1 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8u.ends pmos1*.subckt inv1 in outxmn out in Gnd nmos1xmp out in Vcc pmos1vcc Vcc Gnd Supply.ends inv1*nmos2*.subckt nmos2 n1 n2 n3mn n1 n2

6、 n3 Gnd nch l=0.2u w=1.12u ad=0.56p2 pd=1.12u as=0.56p2 ps=1.12u.ends nmos2*pmos2*.subckt pmos2 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=2.24u ad=1.12p2 pd=2.24u as=1.12p2 ps=2.24u.ends pmos2*.subckt inv2 in outxmn out in Gnd nmos2xmp out in Vcc pmos2vcc Vcc Gnd Supply.ends inv2*nmos3*.subckt nmos3 n1 n

7、2 n3mn n1 n2 n3 Gnd nch l=0.2u w=3.2u ad=1.6p2 pd=3.2u as=1.6p2 ps=3.2u.ends nmos3*pmos3*.subckt pmos3 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=6.4u ad=3.2p2 pd=6.4u as=3.2p2 ps=6.4u.ends pmos3*.subckt inv3 in outxmn out in Gnd nmos3xmp out in Vcc pmos3vcc Vcc Gnd Supply.ends inv3*nmos4*.subckt nmos4 n1

8、 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=9.04u ad=4.52p2 pd=9.04u as=4.52p2 ps=9.04u.ends nmos4*pmos4*.subckt pmos4 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=18.08u ad=9.04p2 pd=18.08u as=9.04p2 ps=18.08u.ends pmos4*.subckt inv4 in outxmn out in Gnd nmos4xmp out in Vcc pmos4vcc Vcc Gnd Supply.ends inv4*main ci

9、rcuit netlistxinv1 in out1 inv1xinv2 out1 out2 inv2xinv3 out2 out3 inv3xinv4 out3 out inv4cl out Gnd 154.24fVin in Gnd 0.9 pulse(0.0 1.8 219p 40p 40p 1100p 2400p).print tran v(in) v(out).end2. Consider the logic network below, which may represent the critical path of a more complex logic block. The

10、output of the。 network is loaded with a capacitance which is 5 times larger than the input capacitance of the first gate, which is a minimum-sized inverter. The effective fanout of the path hence equals F = CL/Cg1 = 5. Using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply, desi

11、gn a circuit simulation scheme to verify (1) the OPTIMAZATIOM parameters of g, f, and s for each of the inverter and gates and The path logical effort G=1*53*53*1=259 The total path effort H=GFB=259*5*1=1259The optimal gate effort h=H14=(1259)14=1.93f1g1=f2g2=f3g3=f4g4=1.93g1=1 g2=53 g3=53 g4=1f1=1.

12、93 f2=1.16 f3=1.16 f4=1.93s1=1 s2=1.16 s3=1.34 s4=2.6在所有的nmos和pmos均采用最小尺寸晶體管的情況下tplh=1.9047E-10 tphl=2.2742E-10 tpd=2.0895E-10在所有所有的mos管尺寸均是前一個mos管尺寸的2倍的情況下tplh=1.8353E-10 tphl=2.4356E-10 tpd=2.1355E-10在參數最優的情況下tplh= 1.7151E-10 tphl=2.2853E-10 tpd=2.0002E-10所以最優參數為上面的推到過程。* SPICE INPUT FILE: Bsim3de

13、mo1.sp-a chain of inverters.param Supply=1.8.lib'C:synopsysHspice_A-2007.09tsmc018mm018.l' TT.option captab.option list node post measout.tran 10p 6000p*.param tdval=10p.meas tran tplh trig v(in) val=0.9 td=tdval rise=2+targ v(out) val=0.9 rise=2.meas tran tphl trig v(in) val=0.9 td=tdval fa

14、ll=2+targ v(out) val=0.9 fall=2.meas tpd param='(tphl+tplh)/2'*macro definitions*nmos1*.subckt nmos1 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=0.4u ad=0.2p2 pd=0.4u as=0.2p2 ps=0.4u.ends nmos1*pmos1*.subckt pmos1 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8u.ends pmo

15、s1*.subckt inv1 in outxmn out in Gnd nmos1xmp out in Vcc pmos1vcc Vcc Gnd Supply.ends inv1*nmos2*.subckt nmos2 n1 n2 n3 n4mn n1 n2 n3 n4 nch l=0.2u w=0.772u ad=0.386p2 pd=0.772u as=0.386p2 ps=0.772u.ends nmos2*pmos2*.subckt pmos2 p1 p2 p3 p4mp p1 p2 p3 p4 pch l=0.2u w=1.544u ad=0.772p2 pd=1.544u as=

16、0.772p2 ps=1.544u.ends pmos2*.subckt nand in1 in2 in3 outxmn1 d1 in1 Gnd Gnd nmos2xmn2 d2 in2 d1 d1 nmos2xmn3 out in3 d2 d2 nmos2xmp1 out in1 Vcc Vcc pmos2xmp2 out in2 Vcc Vcc pmos2xmp3 out in3 Vcc Vcc pmos2vcc Vcc Gnd Supply.ends nand*nmos3*.subckt nmos3 n1 n2 n3 n4mn n1 n2 n3 n4 nch l=0.2u w=0.9u

17、ad=0.45p2 pd=0.9u as=0.45p2 ps=0.9u.ends nmos3*pmos3*.subckt pmos3 p1 p2 p3 p4mp p1 p2 p3 p4 pch l=0.2u w=1.79u ad=0.895p2 pd=1.79u as=0.895p2 ps=1.79u.ends pmos3*.subckt nor in1 in2 outxmn1 out in1 Gnd Gnd nmos3xmn2 out in2 Gnd Gnd nmos3xmp1 out in1 d1 d1 pmos3xmp2 d1 in2 Vcc Vcc pmos3vcc Vcc Gnd S

18、upply.ends nor*nmos4*.subckt nmos4 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=1.044u ad=0.522p2 pd=1.044u as=0.522p2 ps=1.044u.ends nmos4*pmos4*.subckt pmos4 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=2.0764u ad=1.0382p2 pd=2.0764u as=1.0382p2 ps=2.0764u.ends pmos4*.subckt inv2 in outxmn out in Gnd nmos4xmp out

19、 in Vcc pmos4vcc Vcc Gnd Supply.ends inv2*main circuit netlistxinv1 in out1 inv1xnand out1 Vcc Vcc out2 nandxnor out2 Gnd out3 norxinv2 out3 out inv2cl out Gnd 12.05fvcc Vcc Gnd SupplyVin in Gnd 0.9 pulse(0.0 1.8 219p 40p 40p 1100p 2400p).print tran v(in) v(out).end(2) the minimum delay of the chain

20、.在參數最優的情況下tplh= 1.7151E-10 tphl=2.2853E-10 tpd=2.0002E-103. Shown below is a level restore circuit of pass transistor. (1) Without trans3istor Mr,4 verify by using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply that the high input to the signal- restoring inverter only charges

21、 up to VDD - VTn.通過仿真，我們得到V(x)=1.38V，VTn=0.445V，所以Vx1.8V-0.445VVDD-VTn，無法達到VDD的最大值1.8V。(2) After inserting Mr, verify that the high input to the signal-restoring inverter can charge up to VDD.通過仿真得到Vx=VDD=1.8V* SPICE INPUT FILE: Bsim3demo1.sp-a chain of inverters.param Supply=1.8.lib'C:synopsysHspice_A-2007.09tsmc018mm018.l' TT.option captab.option list node post measout.tran 10p 6000p*.param tdval=10p.meas tran tphl trig v(in) val=0.9 td=tdval rise=2+targ v(out) val=0.9 fall=2.meas tran tplh trig v(in) val=0.9 td=tdval fall=2+targ v(out) val=0.9 rise=2.meas tpd param='