1、 問答：Point out design objects in the figure such as :design, cell, reference, port, pin, net, then write a command to set 5 to net ADesign: topReference: ADD DFFCell: U1 U2Port: A B clk sumPin: A B D QNet: A B SINSet_load 5 get_nets Awhy do we not choose to operate all our digital circuits at these l

2、ow supply voltages? 答：1）不加區(qū)分地降低電源電壓雖然對減少能耗能正面影響，但它絕對會使門的延時加大 2）一旦電源電壓和本征電壓（閾值電壓）變得可比擬，DC特性對器件參數(shù)（如晶體管閾值）的變化就變得越來越敏感3）降低電源電壓意味著減少信號擺幅。雖然這通常可以幫助減少系統(tǒng)的內(nèi)部噪聲（如串擾引起的噪聲），但它也使設(shè)計對并不減少的外部噪聲源更加敏感）問道題：1. CMOS靜態(tài)電路中，上拉網(wǎng)絡為什么用PMOS,下拉網(wǎng)絡為什么用NMOS管2. 什么是亞閾值電流，當減少VT時，VGS =0時的亞閾值電流是增加還是減少？3. 什么是速度飽和效應4. CMOS電壓越低，功耗就越少？是不是數(shù)

3、字電路電源電壓越低越好，為什么？5. 如何減少門的傳輸延遲？ P2036. CMOS電路中有哪些類型的功耗？7. 什么是襯墊偏置效應。8. gate-to-channel capacitance CGC,包括哪些部分VirSim有哪幾類窗口3-6. Given the data in Table 0.1 for a short channel NMOS transistor withVDSAT = 0.6 V and k=100 A/V2, calculate VT0, , , 2|f|, and W / L:解答: 對于短溝道器件： 在選擇公式的時候，首先要確定工作區(qū)域，表格中的所有VDS均

4、大于VDSAT，所以不可能工作在線性區(qū)域。如果工作在飽和區(qū)域則： VT 應該滿足 : VGS-VTVDSAT 2-VT0.6 1.4VT這是不可能的，所以可以假設(shè)所有的數(shù)據(jù)都是工作在速度飽和區(qū)域 所以： 由 1&2 () 所以 1,2,3是在速度飽和區(qū)由 2&3 由 2&4 1297/1146=（2-Vt0）2/22/2Vt=0.587V由 2 &5 Vt=0.691V這兩個值都滿足 Vt tpHL 因為 RL=75kW 遠大于有效線性電阻 effective linearized on-resistance of M1.5-5 The next figure shows two implem

5、entations of MOS inverters. The first inverter uses onlyNMOS transistors. Calculate VOH, VOL, VM for each case. 有的參數(shù)參考表1解答：電路 A.VOH: 當 M1關(guān)掉， M2 的閾值是:當下面條件滿足的時候，M2將關(guān)閉: 所以 VOUT=VOH=1.765VVOL: 假設(shè)VIN=VDD=2.5V.我們期望 VOUT 為低, 因此我們可以假設(shè)M2工作在速度飽和區(qū)，而M1工作在線性區(qū)域.因為 ID1= ID2 , 所以 VOUT=VOL=0.263V, 假設(shè)成立VM: 當VM=VIN=V

6、OUT.假設(shè)兩晶體管均工作在速度飽和區(qū)域, 我們得到下面兩個方程: 設(shè) ID1=ID2, 得到 VM=1.269V電路 B.當 VIN=0V, NMOS 關(guān)掉，PMOS 打開，并把VOUT拉到VDD, so VOH=2.5. 同樣, 當 VIN=2.5V, the PMOS關(guān)掉，NMOS 把 VOUT拉到地, 所以VOL=0V.為了計算 VM ： VM=VIN=VOUT.假設(shè)兩晶體管均工作在速度飽和區(qū)域，可以得到下面兩組方程.設(shè) ID3+ ID2 =0 ,可以得到r VM = 1.095V.所以假設(shè)兩晶體管均工作在速度飽和區(qū)域是正確的.5-7 Consider the circuit in F

7、igure 5.5. Device M1 is a standard NMOS device. Device M2 has allthe same properties as M1, except that its device threshold voltage is negative and has a valueof -0.4V. Assume that all the current equations and inequality equations (to determine themode of operation) for the depletion device M2 are

8、 the same as a regular NMOS. Assume thatthe input IN has a 0V to 2.5V swing. ( VDSAT=0.63v)a. Device M2 has its gate terminal connected to its source terminal. If VIN = 0V, what is theoutput voltage? In steady state, what is the mode of operation of device M2 for this input?b. Compute the output vol

9、tage for VIN = 2.5V. You may assume that VOUT is small to simplifyyour calculation. In steady state, what is the mode of operation of device M2 for thisinput?解答 a當 VIN = 0V ， M1則關(guān)掉. M2開， 因為 VGS=0 VTn2.所以沒有電流通過 M2, M2的源漏電壓等于0，故M2工作在線性區(qū)域，所以VOUT=2.5V.Solution b假設(shè) M1工作在線性區(qū)域， M2工作在速度飽和區(qū)域，這就意味：因為Vout很小，所以

10、可以忽略V2out/2,所以可以得到因此我們的假設(shè)是合理的。5-15 Sizing a chain of inverters.a. In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with inputcapacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown in Figure， Assume that the propagation delay of a minimum size inverte

11、r is 70 ps. Also assumethat the input capacitance of a gate is proportional to its size. Determine the sizing of thetwo additional buffer stages that will minimize the propagation delay.b. If you could add any number of stages to achieve the minimum delay, how many stageswould you insert?What is the

12、 propagation delay in this case? 解答a : 當每個buffer的延遲相等的時候，可以得到最小延遲時間.此時每個buffer的尺寸系數(shù)分別為 f, f2 解答 b: 最小延遲時間發(fā)生在 f = e的時候，因此 6-1 Implement the equation using complementary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which

13、 input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance?解答：因為最壞的上拉電阻發(fā)生在，只有一個通路存在output node to Vdd.如： ABCDEFG=1111100 and 0101110.最好的上拉電阻發(fā)生在： ABCDEFG=0000000.最壞的下拉電阻發(fā)生在，只有一個通路存在output node to GND.如： ABCDEFG=0000001 and 0011110.最好的下拉電阻發(fā)生在： ABCDEFG=1111111.5章Assume a

14、n inverter in the generic 0.25 m CMOS technology designed with a PMOS/NMOS ratio of 3.4 and with the NMOS transistor minimum size (W = 0.375 mm, L = 0.25 mm, W/L =1.5). Please compute VIL, VIH, NML, NMH the process parameters is presented in table1解：我們首先計算在VM (= 1.25 V)的增益 所以： VIL=1.2V, VIH=1.3V, NM

15、L= NMH=1.21.How to deduce that the propagation delay of a gate ? p203o Keep capacitances(CL) smallo Increase transistor sizes(W/L)o Increase VDD (see figure 5.22)減小CL: 增加晶體管的W/L，提高VDD2.Determine the sizes of the inverters in the circuit of Figure 5.22, such that the delay between nodes Out and In is

16、 minimized. You may assume that CL = 64 Cg,1 P210Figure 5.22,3. For the circuit of Figure 4.11, assume that a driver with a source resistance of is used to drive a 10 cm long, 1 mm wide Al1 wire. And assume that the total lumped capacitance for this wire equals 11 pF. When applying a step input(with

17、 Vin going from 0 to v), please compute the propagation delay of the circuit. P151 Figure 4.11 解答：4 please analyze intrinsic capacitances of MOSFET transistor ,write out three sources of it, and draw out MOSFET transistor capacitance model. P112答：基本的MOS結(jié)構(gòu)，溝道電荷以及漏和源反向偏置pn結(jié)的耗盡區(qū)。電容器件模型如下：5 .please writ

18、e out the expression of equivalent resistance Req of the circuit in Figure 1 when (dis)charging a capacitor. Assuming that the supply voltage VDD is substantially greater than the velocity-saturation voltage VDSAT of the transistor. the channel-length modulation factor ()cannot be ignored in this an

19、alysis, are known parameters . P105解答：Program1. please write out verilog code and test bench for a 4 bit up-counter Module counter (clk, reset, enable,count);Input clk, reset, enable;Output3:0 count;Reg3:0 count;Always (posedge clk)If (reset=1b1) Count =0; Else if (enable=1b1) Count =count +1;Endmod

20、uleModule counter_tb; Reg clk, reset, enable; Wire3:0 count; Counter U0(clk, reset, enable, count); Initial BeginClk=0;Reset=0;Enable=0; End Always#5 clk=!clk;initial begin $monitor($time, , , “clk=%d reset=%d enable=%d count=%d”, clk,reset,enable,count); #100 $finish end endmodule 2. please write out verilog code and test bench for a bit full adderModule addbit (a, b, ci ,sum,