1、16位CPU的設計要求：此模型機的功能是將存儲區的數據塊復制到另一個存儲區。匯編代碼如下： START：LOADI R1，0010H ;源操作數地址送R1LOADI R2，0030H ；目的操作數地址送R2LOADI R6，002FH ；結束地址送R6NEXT：LOAD R3，R1 ；取數STORE R2，R3 ；存數BRANCHGTI START ；如果R1R6，則轉向STARTINC R1 ；修改源地址INC R2 ；修改目的地址BRANCHI NEXT ；轉向NEXT1. 16位CPU的組成結構2. 指令系統的設計一、 指令格式1) 單字指令格式2) 雙字指令格式二、 指令操作碼操作碼指

2、令功能00001LOAD裝載數據到寄存器00010STORE將寄存器的數據存入到存儲器00100LOADI將立即數裝入到寄存器00101BRANCHI無條件轉移到由立即數指定的地址00110BRANCHGTI如果源寄存器內容大于目的寄存器的內容，則轉移到由立即數指定的地址00111INC寄存器內容加1指令依據以上設計的指令系統，則完成數據塊復制的程序如下：地址機器碼指令 功能說明0000H0001H2001H0010HLOADI R1，0010H源操作數地址送R10002H0003H2002H0030HLOADI R2，0030H目的操作數地址送R20004H0005H2006H002FHLO

3、ADI R6，002FH結束地址送R60006H080BHLOAD R3，R1取數0007H101AHSTORE R2，R3存數0008H 0009H300EH0000HBRANCHGTI 0000如果R1大于R6，則轉向地址0000000AH3801HINC R1修改源地址000BH3802HINC R2修改目的地址000CH000DH2800H0006HBRANCHI 0006H轉向00006H，實現循環3. VHDL設計一、 程序包：說明運算器的功能、移動寄存器的操作、比較器的比較類型和用于CPU控制的狀態類型。library ieee;use ieee.std_logic_1164.a

4、ll;use ieee.std_logic_arith.all;package cpu_lib is subtype t_shift is unsigned (3 downto 0);constant shftpass :unsigned(3 downto 0):=0000;constant sftl :unsigned(3 downto 0):=0001;constant sftr:unsigned(3 downto 0):=0010;constant rotl :unsigned(3 downto 0):=0011;constant rotr :unsigned(3 downto 0):=

5、0100;subtype t_alu is unsigned(3 downto 0);constant alupass :unsigned(3 downto 0):=0000;constant andOp :unsigned(3 downto 0):=0001;constant orOp:unsigned(3 downto 0):=0010;constant notOp :unsigned(3 downto 0):=0011;constant xorOp :unsigned(3 downto 0):=0100;constant plus :unsigned(3 downto 0):=0101;

6、constant alusub :unsigned(3 downto 0):=0110;constant inc :unsigned(3 downto 0):=0111;constant dec :unsigned(3 downto 0):=1000;constant zero:unsigned(3 downto 0):=1001;subtype t_comp is unsigned 2 downto 0);constant eq :unsigned(2 downto 0):=000;constant neq :unsigned(2 downto 0):=001;constant gt:uns

7、igned(2 downto 0):=010;constant gte :unsigned(2 downto 0):=011;constant lt :unsigned(2 downto 0):=100;constant lte :unsigned(2 downto 0):=101;subtype t_reg is std_logic_vector(2 downto 0);type state is (reset1,reset2,reset3,reset4,reset5,reset6,execute,nop,load,store,move,load2,load3,load4,store2,st

8、ore3,store4,move2,move3,move4,incPc,incPc2,incPc3,incPc4,incPc5,incPc6,loadPc,loadPc2,loadPc3,loadPc4,bgtI2,bgtI3,bgtI4,bgtI5,bgtI6,bgtI7,bgtI8,bgtI9,bgtI10,braI2,braI3,braI4,braI5,braI6,loadI2,loadI3,loadI4,loadI5,loadI6,inc2,inc3,inc4);subtype bit16 is std_logic_vector(15 downto 0);end cpu_lib;二、基

9、本部件的設計1) 運算器的設計 功能library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.cpu_lib.all;entity alu is port(a,b:in bit16;sel:in t_alu;c:out bit16);end alu;architecture rt1 of alu is beginprocess(a,b,sel)begincase sel iswhen alupass= c c c c c c c c c c c if a=b then compout =1

10、 after 1ns;else compout if a/=b then compout =1 after 1ns;else compout if ab then compout =1 after 1ns;else compout if a=b then compout =1 after 1ns;else compout if ab then compout =1 after 1ns;else compout if a=b then compout =1 after 1ns;else compout compout y y y y y y=0000000000000000 after 1 ns

11、;end case;end process;end rt1;4) 寄存器library ieee;use ieee.std_logic_1164.all;use work.cpu_lib.all;entity reg is port(a:in bit16;clk:in std_logic;q:out bit16);end reg;architecture rt1 of reg isbeginprocessbeginwait until clkevent and clk=1;q=a after 1ns;end process;end rt1;5) 寄存器組library ieee;use iee

12、e.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.cpu_lib.all;entity regarray is port(data:in bit16;sel:in t_reg;en,clk:in std_logic;q:out bit16);end regarray;architecture rt1 of regarray is type t_ram is array (0 to 7) of bit16;signal temp_data:bit16;beginprocess(clk,sel)variable ramdat

13、a:t_ram;beginif clkevent and clk=1 then ramdata(conv_integer(sel):=data;end if;temp_data=ramdata(conv_integer(sel) after 1 ns;end process;process(en,temp_data)beginif en=1 then q=temp_data after 1 ns; else q=ZZZZZZZZZZZZZZZZ after 1 ns;end if;end process;end rt1;6) 三態寄存器library ieee;use ieee.std_log

14、ic_1164.all;use ieee.std_logic_unsigned.all;use work.cpu_lib.all;entity trireg isport(a:in bit16;en,clk:in std_logic;q:out bit16);end trireg;architecture rt1 of trireg issignal val:bit16;beginprocessbeginwait until clkevent and clk=1;val=a;end process;process(en,val)beginif en=1 then q=val after 1 n

15、s;elsif en=0 then q=ZZZZZZZZZZZZZZZZ after 1 ns;else q=XXXXXXXXXXXXXXXX after 1 ns;end if;end process;end rt1;7) 控制器采用狀態機實現library IEEE;use IEEE.std_logic_1164.all;use work.cpu_lib.all;entity control isport( clock,reset,compout:in std_logic; instrReg:in bit16;progCntrWr,progCntrRd,addrRegWr,outRegWr

16、,outRegRd:out std_logic;shiftSel:out t_shift; aluSel:out t_alu; compSel:out t_comp;opRegRd,opRegWr,instrWr,regRd,regWr,rw,vma:out std_logic;regSel:out t_reg );end control;architecture rtl of control issignal current_state, next_state : state;beginprocess( current_state, instrReg, compout)beginprogCn

17、trWr = 0; progCntrRd = 0; addrRegWr = 0; outRegWr = 0;outRegRd = 0; shiftSel = shftpass; aluSel = alupass; compSel = eq;opRegRd = 0; opRegWr = 0; instrWr = 0; regSel = 000;regRd = 0; regWr = 0; rw = 0; vma aluSel=zero after 1 ns; shiftSel=shftpass; next_state aluSel=zero; shiftSel=shftpass; outRegWr

18、=1; next_state outRegRd=1; next_state outRegRd=1; progCntrWr=1;addrRegWr=1; next_state vma=1; rw = 0; next_state vma=1; rw=0;instrWr=1; next_state case instrReg(15 downto 11) iswhen 00000 = next_state regSel=instrReg(5 downto 3); regRd=1;next_state regSel=instrReg(2 downto 0); regRd=1;next_state reg

19、Sel=instrReg(5 downto 3); regRd=1; aluSel=alupass;shiftSel=shftpass; next_state progcntrRd=1; alusel=inc; shiftsel=shftpass;next_state progcntrRd=1; alusel=inc; shiftsel=shftpass;next_state regSel=instrReg(5 downto 3); regRd=1;next_state regSel=instrReg(2 downto 0); regRd=1; alusel=inc;shiftsel=shft

20、pass; next_statenext_state regSel = instrReg(5 downto 3); regRd = 1;addrregWr = 1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; regSel = instrReg(2 downto 0);regWr = 1; next_state regSel = instrReg(2 downto 0); regRd = 1;addrregWr = 1; next_state regSel = instrReg(5 downto 3); regRd = 1;n

21、ext_state regSel = instrReg(5 downto 3); regRd = 1; rw = 1; next_state regSel = instrReg(5 downto 3); regRd = 1;aluSel =alupass;shiftsel = shftpass; outRegWr = 1; next_state outRegRd = 1; next_state outRegRd = 1;regSel = instrReg(2 downto 0); regWr = 1; next_state progcntrRd = 1; alusel = inc; shift

22、sel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd = 1; progcntrWr=1; addrregWr=1;next_state vma = 1; rw = 0; next_state vma = 1; rw = 0;regSel = instrReg(2 downto 0);regWr = 1; next_state progcntrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1;

23、 next_state outregRd=1; progcntrWr=1; addrregWr=1;next_state vma=1; rw=0; next_state vma = 1; rw = 0;progcntrWr = 1; next_state regSel = instrReg(5 downto 3); regRd = 1;opRegWr = 1; next_state opRegRd = 1; regSel = instrReg(2 downto 0);regRd = 1; compsel = gt; next_state opRegRd = 1 after 1 ns;regSe

24、l = instrReg(2 downto 0); regRd = 1; compsel = gt;if compout = 1 then next_state = bgtI5;else next_state progcntrRd=1; alusel=inc; shiftSel=shftpass;next_state progcntrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd = 1;progcntrWr = 1; addrregWr =

25、 1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; progcntrWr = 1; next_state regSel = instrReg(2 downto 0); regRd = 1; alusel = inc;shiftsel = shftpass; outregWr = 1; next_state outregRd = 1; next_state outregRd = 1; regsel = instrReg(2 downto 0);regWr = 1; next_state progcntrRd = 1; next_state progcntrRd = 1; addrRegWr = 1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; instr