1、VHDL程序設計數字電子表1 VHDL程序設計數字電子表2 6 個七段數碼管個七段數碼管 SEGOUT ( 8 )( 8 ) CLR 時鐘顯示時鐘顯示 電路方框圖電路方框圖 CP FPGA SELOUT ( 6 )( 6 ) VHDL程序設計數字電子表3 24 進進 制制 計數器計數器 60 進進 制制 計數器計數器 60 進進 制制 計數器計數器 BCD 七段譯碼電路七段譯碼電路 BCD 選擇選擇 BCD(8)(8)BIN(6)(6) 6 個七段數碼管個七段數碼管 掃描電路掃描電路 S(3)(3) SEG (8)(8) NUM(4)(4) BCD (3-0)(3-0) BCD (7-4)(7

2、-4) ENB (0)(0) ENB (1)(1) ENB (2)(2) DBHDBM DBS BIN ( 6 )( 6 ) 時鐘顯示時鐘顯示 電路方框圖電路方框圖 SEC CLR CYH CYS CYM 分頻器分頻器 CP 38 譯譯 碼碼 VHDL程序設計數字電子表4 24 進進 制制 計數器計數器 60 進進 制制 計數器計數器 60 進進 制制 計數器計數器 BCD 七段譯碼電路七段譯碼電路 BCD 選擇選擇 BCD(8)(8)BIN(6)(6) 6 個七段數碼管個七段數碼管 掃描電路掃描電路 S(3)(3) SEG (8)(8) NUM(4)(4) BCD (3-0)(3-0) BC

3、D (7-4)(7-4) ENB (0)(0) ENB (1)(1) ENB (2)(2) DBHDBM DBS BIN ( 6 )( 6 ) 時鐘顯示時鐘顯示 電路方框圖電路方框圖 SEC CLR CYH CYS CYM 分頻器分頻器 CP 38 譯譯 碼碼 VHDL程序設計數字電子表5 PROCESS (CP)PROCESS (CP) BeginBegin IF CPEvent AND CP=1 thenIF CPEvent AND CP=1 then DLY = Q(21)DLY = Q(21); ; Q = Q+1;Q = Q+1; END IF;END IF; END PROCESS

4、;END PROCESS; VHDL程序設計數字電子表6 Free_Counter : BlockFree_Counter : Block Signal Signal Q Q: STD_LOGIC_VECTOR(24 DOWNTO 0);: STD_LOGIC_VECTOR(24 DOWNTO 0); Signal DLY Signal DLY : STD_LOGIC;: STD_LOGIC; BeginBegin PROCESS (CP)PROCESS (CP) BeginBegin IF CPEvent AND CP=1 thenIF CPEvent AND CP=1 then DLY =

5、 Q(21);DLY = Q(21); Q = Q+1;Q = Q+1; END IF;END IF; END PROCESS;END PROCESS; SEC = Q(21) AND NOT DLY;SEC = Q(21) AND NOT DLY;-about 1Hz -about 1Hz S = Q(15 DOWNTO 13);S = Q(15 DOWNTO 13);-about 250 Hz-about 250 Hz ENB ENB = 001 WHEN (S=0 OR S=1) ELSE= 001 WHEN (S=0 OR S=1) ELSE 010 WHEN (S=2 OR S=3)

6、 ELSE010 WHEN (S=2 OR S=3) ELSE 100 WHEN (S=4 OR S=5) ELSE100 WHEN (S=4 OR S=5) ELSE 000;000; BIN BIN = DBS WHEN ENB = 001 ELSE= DBS WHEN ENB = 001 ELSE DBM WHEN ENB = 010 ELSEDBM WHEN ENB = 010 ELSE DBH WHEN ENB = 100 ELSEDBH WHEN ENB = 100 ELSE 000000;000000; End Block Free_Counter;End Block Free_

7、Counter; VHDL程序設計數字電子表7 -主文件聲明代碼主文件聲明代碼 COMPONENT COUNTER60COMPONENT COUNTER60 PORT(PORT( CPCP: IN: IN STD_LOGIC;STD_LOGIC; BINBIN: OUT: OUTSTD_LOGIC_VECTOR (5 DOWNTO 0);STD_LOGIC_VECTOR (5 DOWNTO 0); S S: IN: IN STD_LOGIC;STD_LOGIC; CLRCLR: IN : IN STD_LOGIC;STD_LOGIC; ECEC: IN STD_LOGIC;: IN STD_L

8、OGIC; CY60CY60 : OUT STD_LOGIC: OUT STD_LOGIC );); END COMPONENT;END COMPONENT; VHDL程序設計數字電子表8 - - 子文件定義代碼子文件定義代碼 -* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * LIBRARY IEEE;LIBRARY IEEE; USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_UNS

9、IGNED.ALL; -* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ENTITY COUNTER60 ISENTITY COUNTER60 IS PORT(PORT( CP CP : : IN STD_LOGIC;IN STD_LOGIC; BINBIN: : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);OUT STD_LOGIC_VECTOR (5 DOWNTO 0); S S : : IN STD_LOG

10、IC;IN STD_LOGIC; CLR CLR : : IN STD_LOGIC;IN STD_LOGIC; EC EC : : IN STD_LOGIC;IN STD_LOGIC; CY60 CY60 : : OUT STD_LOGICOUT STD_LOGIC );); END COUNTER60;END COUNTER60; VHDL程序設計數字電子表9 - - 子文件定義代碼子文件定義代碼 ARCHITECTURE a OF COUNTER60 ISARCHITECTURE a OF COUNTER60 IS SIGNAL Q : STD_LOGIC_VECTOR (5 DOWNTO

11、 0) ;SIGNAL Q : STD_LOGIC_VECTOR (5 DOWNTO 0) ; SIGNAL RST, DLY : STD_LOGIC;SIGNAL RST, DLY : STD_LOGIC; BEGINBEGIN PROCESS (CP,RST)PROCESS (CP,RST) BEGINBEGIN IF RST = 1 THENIF RST = 1 THEN Q = 000000;Q = 000000; ELSIF CPevent AND CP = 1 THENELSIF CPevent AND CP = 1 THEN DLY = Q(5);DLY = Q(5); IF E

12、C = 1 THENIF EC = 1 THEN Q = Q+1;Q = Q+1; END IF; END IF; END IF;END IF; END PROCESS;END PROCESS; CY60 = CY60 = NOT Q(5) AND DLY;NOT Q(5) AND DLY; RST = 1 WHEN Q=60 OR CLR=1 ELSERST = 1 WHEN Q=60 OR CLR=1 ELSE 0; 0; BIN = BIN = Q Q WHEN S = 1 ELSE WHEN S = 1 ELSE 000000; 000000; END a;END a; VHDL程序設

13、計數字電子表10 -主文件聲明代碼主文件聲明代碼 COMPONENT COUNTER24COMPONENT COUNTER24 PORT(PORT( CPCP: IN: IN STD_LOGIC;STD_LOGIC; BINBIN: OUT: OUTSTD_LOGIC_VECTOR (5 DOWNTO 0);STD_LOGIC_VECTOR (5 DOWNTO 0); S S: IN: IN STD_LOGIC;STD_LOGIC; CLRCLR: IN : IN STD_LOGIC;STD_LOGIC; ECEC: IN STD_LOGIC;: IN STD_LOGIC; CY60CY60

14、: OUT STD_LOGIC: OUT STD_LOGIC );); END COMPONENT;END COMPONENT; VHDL程序設計數字電子表11 - - 子文件定義代碼子文件定義代碼 -* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * LIBRARY IEEE;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.ST

15、D_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; -* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ENTITY COUNTER24 ISENTITY COUNTER24 IS PORT(PORT( CP CP : : IN STD_LOGIC;IN STD_LOGIC; BINBIN: : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);OUT STD_LO

16、GIC_VECTOR (5 DOWNTO 0); S S : : IN STD_LOGIC;IN STD_LOGIC; CLR CLR : : IN STD_LOGIC;IN STD_LOGIC; EC EC : : IN STD_LOGIC;IN STD_LOGIC; CY24 CY24 : : OUT STD_LOGICOUT STD_LOGIC );); END COUNTER24;END COUNTER24; VHDL程序設計數字電子表12 - - 子文件定義代碼子文件定義代碼 ARCHITECTURE a OF COUNTER24 ISARCHITECTURE a OF COUNTE

17、R24 IS SIGNAL Q SIGNAL Q : : STD_LOGIC_VECTOR (4 DOWNTO 0) ;STD_LOGIC_VECTOR (4 DOWNTO 0) ; SIGNAL RST, DLY : SIGNAL RST, DLY : STD_LOGIC;STD_LOGIC; BEGINBEGIN PROCESS (CP,RST)PROCESS (CP,RST) BEGINBEGIN IF RST = 1 THENIF RST = 1 THEN Q = 00000;Q = 00000; ELSIF CPevent AND CP = 1 THENELSIF CPevent A

18、ND CP = 1 THEN DLY = Q(4);DLY = Q(4); IF EC = 1 THENIF EC = 1 THEN Q = Q+1;Q = Q+1; END IF; END IF; END IF;END IF; END PROCESS;END PROCESS; CY24 = CY24 = NOT Q(4) AND DLY;NOT Q(4) AND DLY; RST = 1 WHEN Q=24 OR CLR=1 ELSERST = 1 WHEN Q=24 OR CLR=1 ELSE 0; 0; BIN = BIN = (0 000000; END a;END a; VHDL程序

19、設計數字電子表13 Binary_BCD : BlockBinary_BCD : Block BEGINBEGIN BCD =BCD =00000000 WHEN BIN = 0 ELSE00000000 WHEN BIN = 0 ELSE 00000001 WHEN BIN = 1 ELSE00000001 WHEN BIN = 1 ELSE 00000010 WHEN BIN = 2 ELSE00000010 WHEN BIN = 2 ELSE 00000011 WHEN BIN = 3 ELSE00000011 WHEN BIN = 3 ELSE 00000100 WHEN BIN =

20、4 ELSE00000100 WHEN BIN = 4 ELSE 00000101 WHEN BIN = 5 ELSE00000101 WHEN BIN = 5 ELSE 00000110 WHEN BIN = 6 ELSE00000110 WHEN BIN = 6 ELSE 00000111 WHEN BIN = 7 ELSE00000111 WHEN BIN = 7 ELSE 00001000 WHEN BIN = 8 ELSE00001000 WHEN BIN = 8 ELSE 00001001 WHEN BIN = 9 ELSE00001001 WHEN BIN = 9 ELSE 00

21、010000 WHEN BIN = 10 ELSE00010000 WHEN BIN = 10 ELSE 00010001 WHEN BIN = 11 ELSE00010001 WHEN BIN = 11 ELSE 00010010 WHEN BIN = 12 ELSE00010010 WHEN BIN = 12 ELSE 00010011 WHEN BIN = 13 ELSE00010011 WHEN BIN = 13 ELSE 00010100 WHEN BIN = 14 ELSE00010100 WHEN BIN = 14 ELSE 00010101 WHEN BIN = 15 ELSE

22、00010101 WHEN BIN = 15 ELSE 00010110 WHEN BIN = 16 ELSE00010110 WHEN BIN = 16 ELSE 00010111 WHEN BIN = 17 ELSE00010111 WHEN BIN = 17 ELSE 00011000 WHEN BIN = 18 ELSE00011000 WHEN BIN = 18 ELSE 00011001 WHEN BIN = 19 ELSE00011001 WHEN BIN = 19 ELSE 00100000 WHEN BIN = 20 ELSE00100000 WHEN BIN = 20 EL

23、SE 00100001 WHEN BIN = 21 ELSE00100001 WHEN BIN = 21 ELSE 00100010 WHEN BIN = 22 ELSE00100010 WHEN BIN = 22 ELSE 00100011 WHEN BIN = 23 ELSE00100011 WHEN BIN = 23 ELSE 00100100 WHEN BIN = 24 ELSE00100100 WHEN BIN = 24 ELSE 00100101 WHEN BIN = 25 ELSE00100101 WHEN BIN = 25 ELSE 00100110 WHEN BIN = 26

24、 ELSE00100110 WHEN BIN = 26 ELSE 00100111 WHEN BIN = 27 ELSE00100111 WHEN BIN = 27 ELSE VHDL程序設計數字電子表14 00101000 WHEN BIN = 28 ELSE00101000 WHEN BIN = 28 ELSE 00101001 WHEN BIN = 29 ELSE00101001 WHEN BIN = 29 ELSE 00110000 WHEN BIN = 30 ELSE00110000 WHEN BIN = 30 ELSE 00110001 WHEN BIN = 31 ELSE0011

25、0001 WHEN BIN = 31 ELSE 00110010 WHEN BIN = 32 ELSE00110010 WHEN BIN = 32 ELSE 00110011 WHEN BIN = 33 ELSE00110011 WHEN BIN = 33 ELSE 00110100 WHEN BIN = 34 ELSE00110100 WHEN BIN = 34 ELSE 00110101 WHEN BIN = 35 ELSE00110101 WHEN BIN = 35 ELSE 00110110 WHEN BIN = 36 ELSE00110110 WHEN BIN = 36 ELSE 0

26、0110111 WHEN BIN = 37 ELSE00110111 WHEN BIN = 37 ELSE 00111000 WHEN BIN = 38 ELSE00111000 WHEN BIN = 38 ELSE 00111001 WHEN BIN = 39 ELSE00111001 WHEN BIN = 39 ELSE 01000000 WHEN BIN = 40 ELSE01000000 WHEN BIN = 40 ELSE 01000001 WHEN BIN = 41 ELSE01000001 WHEN BIN = 41 ELSE 01000010 WHEN BIN = 42 ELS

27、E01000010 WHEN BIN = 42 ELSE 01000011 WHEN BIN = 43 ELSE01000011 WHEN BIN = 43 ELSE 01000100 WHEN BIN = 44 ELSE01000100 WHEN BIN = 44 ELSE 01000101 WHEN BIN = 45 ELSE01000101 WHEN BIN = 45 ELSE 01000110 WHEN BIN = 46 ELSE01000110 WHEN BIN = 46 ELSE 01000111 WHEN BIN = 47 ELSE01000111 WHEN BIN = 47 E

28、LSE 01001000 WHEN BIN = 48 ELSE01001000 WHEN BIN = 48 ELSE 01001001 WHEN BIN = 49 ELSE01001001 WHEN BIN = 49 ELSE 01010000 WHEN BIN = 50 ELSE01010000 WHEN BIN = 50 ELSE 01010001 WHEN BIN = 51 ELSE01010001 WHEN BIN = 51 ELSE 01010010 WHEN BIN = 52 ELSE01010010 WHEN BIN = 52 ELSE 01010011 WHEN BIN = 5

29、3 ELSE01010011 WHEN BIN = 53 ELSE 01010100 WHEN BIN = 54 ELSE01010100 WHEN BIN = 54 ELSE 01010101 WHEN BIN = 55 ELSE01010101 WHEN BIN = 55 ELSE 01010110 WHEN BIN = 56 ELSE01010110 WHEN BIN = 56 ELSE 01010111 WHEN BIN = 57 ELSE01010111 WHEN BIN = 57 ELSE 01011000 WHEN BIN = 58 ELSE01011000 WHEN BIN =

30、 58 ELSE 01011001 WHEN BIN = 59 ELSE01011001 WHEN BIN = 59 ELSE 00000000;00000000; END Block Binary_BCD;END Block Binary_BCD; VHDL程序設計數字電子表15 SELECT_BCD : BlockSELECT_BCD : Block BEGINBEGIN NUM = NUM = BCD(3 DOWNTO 0) BCD(3 DOWNTO 0) WHEN (WHEN (S=0 OR S=2 OR S=4S=0 OR S=2 OR S=4) ELSE) ELSE BCD(7 D

31、OWNTO 4);BCD(7 DOWNTO 4); End Block SELECT_BCD;End Block SELECT_BCD; VHDL程序設計數字電子表16 SEVEN_SEGMENT : BlockSEVEN_SEGMENT : Block BeginBegin -gfedcba -gfedcba SEG = SEG = 0111111 WHEN NUM = 0 ELSE0111111 WHEN NUM = 0 ELSE 0000110 WHEN NUM = 1 ELSE0000110 WHEN NUM = 1 ELSE 1011011 WHEN NUM = 2 ELSE1011

32、011 WHEN NUM = 2 ELSE 1001111 WHEN NUM = 3 ELSE1001111 WHEN NUM = 3 ELSE 1100110 WHEN NUM = 4 ELSE1100110 WHEN NUM = 4 ELSE 1101101 WHEN NUM = 5 ELSE1101101 WHEN NUM = 5 ELSE 1111101 WHEN NUM = 6 ELSE1111101 WHEN NUM = 6 ELSE 0000111 WHEN NUM = 7 ELSE0000111 WHEN NUM = 7 ELSE 1111111 WHEN NUM = 8 EL

33、SE1111111 WHEN NUM = 8 ELSE 1101111 WHEN NUM = 9 ELSE1101111 WHEN NUM = 9 ELSE 1110111 WHEN NUM = 10 ELSE1110111 WHEN NUM = 10 ELSE 1111100 WHEN NUM = 11 ELSE1111100 WHEN NUM = 11 ELSE 0111001 WHEN NUM = 12 ELSE0111001 WHEN NUM = 12 ELSE 1011110 WHEN NUM = 13 ELSE1011110 WHEN NUM = 13 ELSE 1111001 W

34、HEN NUM = 14 ELSE1111001 WHEN NUM = 14 ELSE 1110001 WHEN NUM = 15 ELSE1110001 WHEN NUM = 15 ELSE 0000000;0000000; End Block SEVEN_SEGMENT;End Block SEVEN_SEGMENT; VHDL程序設計數字電子表17 CP IN D CP Q #Q D CP Q #Q OUT VHDL程序設計數字電子表18 時序圖：時序圖： CP IN Q1 Q2 OUT CP IN D CP Q #Q D CP Q #Q OUT VHDL程序設計數字電子表19 CP I

35、N D CP Q #Q D CP Q #Q EC CLK Q VHDL程序設計數字電子表20 l機械開關的抖動存在三種情況：按下時有抖動，松開時機械開關的抖動存在三種情況：按下時有抖動，松開時 也有抖動；按下時有抖動，松開時無抖動；按下時無抖也有抖動；按下時有抖動，松開時無抖動；按下時無抖 動，松開時有抖動。機械開關的抖動波形、抖動次數、動，松開時有抖動。機械開關的抖動波形、抖動次數、 抖動時間都是隨機的，并不是每次都會產生抖動。抖動時間都是隨機的，并不是每次都會產生抖動。 l不同開關的最長抖動時間也不同。抖動時間的長短和機不同開關的最長抖動時間也不同。抖動時間的長短和機 械開關特性有關，一般

36、為械開關特性有關，一般為5ms到到10ms。但是，某些開關。但是，某些開關 的抖動時間長達的抖動時間長達20ms，甚至更長。所以，在具體設計中，甚至更長。所以，在具體設計中 要具體分析，根據實際情況來調整設計。要具體分析，根據實際情況來調整設計。 l彈跳現象以及彈跳消除如圖彈跳現象以及彈跳消除如圖1 所示，雖然只是按下按鍵所示，雖然只是按下按鍵 一次后放掉，結果在按鍵信號穩定先后竟出現了多個段一次后放掉，結果在按鍵信號穩定先后竟出現了多個段 脈沖，如果將這樣的信號直接送到計數器之類的時序電脈沖，如果將這樣的信號直接送到計數器之類的時序電 路，結果將可能發生計數超過一次以上的誤動作，從而路，結果

37、將可能發生計數超過一次以上的誤動作，從而 誤以為鍵盤按了多次。因此，必須加上彈跳消除電路，誤以為鍵盤按了多次。因此，必須加上彈跳消除電路， 除去短脈沖，避免誤操作的發生。除去短脈沖，避免誤操作的發生。 VHDL程序設計數字電子表21 VHDL程序設計數字電子表22 CP IN D CP Q #Q D CP Q #Q S R Q #Q D O U T VHDL程序設計數字電子表23 -* LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;

38、 -* ENTITY Debunce is PORT( test_S: OUT STD_LOGIC; CP: IN STD_LOGIC; Key : IN STD_LOGIC; DLY_OUT : OUT STD_LOGIC; DIF_OUT: OUT STD_LOGIC ); END Debunce; -* ARCHITECTURE a OF Debunce IS VHDL程序設計數字電子表24 SIGNAL SAMPLE, DLY, NDLY, DIFF: STD_LOGIC; - Binary BEGIN test_S = SAMPLE; Free_Counter : Block- 計數

39、器計數器 Signal D0 : STD_LOGIC; Begin PROCESS (CP)- 計數器計數計數器計數 Begin IF CPEvent AND CP=1 then D0 = Q(4); Q = Q+1; END IF; END PROCESS; SAMPLE 25HZ脈沖脈沖 -SAMPLE = Q(1) AND NOT D0; END Block Free_Counter; VHDL程序設計數字電子表25 Debunce : Block- Debounce SIGNAL D0, D1, S, R : STD_LOGIC; Begin Process (CP) Begin IF

40、 CPEVENT AND CP=1 THEN IF SAMPLE = 1 THEN D1 = D0; D0 = KEY;- Two Stage Delay S = D0 AND D1;- Generate S、R R = NOT D0 AND NOT D1; END IF; END IF; End Process; DLY = R NOR NDLY;- Debounce O/P NDLY =S NOR DLY; DLY_OUT = DLY; End Block Debunce; VHDL程序設計數字電子表26 Differential : Block-Differential Signal D

41、1,D0 : STD_LOGIC; BEGIN Process (CP) Begin IF CPEVENT AND CP=1 THEN D1 = D0; D0 = DLY;- Two State Delay END IF; End Process; DIFF = D0 AND NOT D1;- Differential END Block Differential; DIF_OUT = DIFF;- Differential O/P END a; VHDL程序設計數字電子表27 LIBRARY IEEE;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;USE

42、 IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Timer_Dsp isENTITY Timer_Dsp is PORT(PORT( CP CP: IN STD_LOGIC;: IN STD_LOGIC; SEGOUT SEGOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); SELOUT SELOUT: OUT STD_LOGIC_VECTOR(5 D

43、OWNTO 0);: OUT STD_LOGIC_VECTOR(5 DOWNTO 0); CLEAR CLEAR : IN STD_LOGIC: IN STD_LOGIC );); END Timer_Dsp;END Timer_Dsp; ARCHITECTURE a OF Timer_Dsp ISARCHITECTURE a OF Timer_Dsp IS COMPONENT COUNTER60COMPONENT COUNTER60 PORT(PORT( CPCP: IN: INSTD_LOGIC;STD_LOGIC; BINBIN: OUT: OUTSTD_LOGIC_VECTOR (5

44、DOWNTO 0);STD_LOGIC_VECTOR (5 DOWNTO 0); S S: IN: INSTD_LOGIC;STD_LOGIC; CLRCLR: IN : IN STD_LOGIC;STD_LOGIC; ECEC: IN STD_LOGIC;: IN STD_LOGIC; CY60CY60: OUT STD_LOGIC: OUT STD_LOGIC );); END COMPONENT;END COMPONENT; COMPONENT COUNTER24COMPONENT COUNTER24 PORT(PORT( CPCP: IN: INSTD_LOGIC;STD_LOGIC;

45、 BINBIN: OUT: OUTSTD_LOGIC_VECTOR (5 DOWNTO 0);STD_LOGIC_VECTOR (5 DOWNTO 0); S S: IN: INSTD_LOGIC;STD_LOGIC; CLRCLR: IN : IN STD_LOGIC;STD_LOGIC; ECEC: IN STD_LOGIC;: IN STD_LOGIC; CY24CY24: OUT STD_LOGIC: OUT STD_LOGIC );); END COMPONENT;END COMPONENT; VHDL程序設計數字電子表28 SIGNAL BIN SIGNAL BIN : STD_L

46、OGIC_VECTOR (5 DOWNTO 0);: STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL DBS SIGNAL DBS : STD_LOGIC_VECTOR (5 DOWNTO 0);: STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL DBM SIGNAL DBM : STD_LOGIC_VECTOR (5 DOWNTO 0);: STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL DBH SIGNAL DBH : STD_LOGIC_VECTOR (5 DOWNTO 0);: STD_LOGIC_VE

47、CTOR (5 DOWNTO 0); SIGNAL ENB SIGNAL ENB : STD_LOGIC_VECTOR (2 DOWNTO 0);: STD_LOGIC_VECTOR (2 DOWNTO 0); SIGNAL SECSIGNAL SEC: STD_LOGIC;: STD_LOGIC; SIGNAL BCD SIGNAL BCD : STD_LOGIC_VECTOR (7 DOWNTO 0);: STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL CLRSIGNAL CLR: STD_LOGIC;: STD_LOGIC; SIGNAL CYS,CYM,CY

48、HSIGNAL CYS,CYM,CYH: STD_LOGIC;: STD_LOGIC; Signal S Signal S : STD_LOGIC_VECTOR(2 DOWNTO 0);: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL NUM SIGNAL NUM : STD_LOGIC_VECTOR( 3 DOWNTO 0);: STD_LOGIC_VECTOR( 3 DOWNTO 0); SIGNAL SEGSIGNAL SEG: STD_LOGIC_VECTOR( 6 DOWNTO 0);: STD_LOGIC_VECTOR( 6 DOWNTO 0); BEG

49、INBEGIN VHDL程序設計數字電子表29 Connection : BlockConnection : Block BeginBegin U1: COUNTER60 PORT MAP(CP,DBS,ENB(0),CLR,SEC,CYS);U1: COUNTER60 PORT MAP(CP,DBS,ENB(0),CLR,SEC,CYS); U2: COUNTER60 PORT MAP(CP,DBM,ENB(1),CLR,CYS,CYM);U2: COUNTER60 PORT MAP(CP,DBM,ENB(1),CLR,CYS,CYM); U3: COUNTER24 PORT MAP(CP,

50、DBH,ENB(2),CLR,CYM,CYH);U3: COUNTER24 PORT MAP(CP,DBH,ENB(2),CLR,CYM,CYH); CLR = CLEAR;CLR = CLEAR; SELOUT = S;SELOUT = S; SEGOUT(6 DOWNTO 0) = SEG;SEGOUT(6 DOWNTO 0) = SEG; SEGOUT(7) = 0;SEGOUT(7) = 0; End Block Connection;End Block Connection; VHDL程序設計數字電子表30 Free_Counter : BlockFree_Counter : Blo

51、ck Signal Signal Q Q: STD_LOGIC_VECTOR(24 DOWNTO 0);: STD_LOGIC_VECTOR(24 DOWNTO 0); Signal DLY Signal DLY : STD_LOGIC;: STD_LOGIC; BeginBegin PROCESS (CP)PROCESS (CP)- - 計數器計數計數器計數 BeginBegin IF CPEvent AND CP=1 thenIF CPEvent AND CP=1 then DLY = Q(21);DLY = Q(21); Q = Q+1;Q = Q+1; END IF;END IF; E

52、ND PROCESS;END PROCESS; SEC = Q(21) AND NOT DLY;SEC = Q(21) AND NOT DLY;-about 1Hz -about 1Hz S = Q(15 DOWNTO 13);S = Q(15 DOWNTO 13);-about 250 Hz-about 250 Hz ENB = 001 WHEN (S=0 OR S=1) ELSEENB = 001 WHEN (S=0 OR S=1) ELSE 010 WHEN (S=2 OR S=3) ELSE010 WHEN (S=2 OR S=3) ELSE 100 WHEN (S=4 OR S=5)

53、 ELSE100 WHEN (S=4 OR S=5) ELSE 000;000; BIN = DBS WHEN ENB = 001 ELSEBIN = DBS WHEN ENB = 001 ELSE DBM WHEN ENB = 010 ELSEDBM WHEN ENB = 010 ELSE DBH WHEN ENB = 100 ELSEDBH WHEN ENB = 100 ELSE 000000;000000; End Block Free_Counter;End Block Free_Counter; VHDL程序設計數字電子表31 Binary_BCD : BlockBinary_BCD

54、 : Block BEGINBEGIN BCD =BCD =00000000 WHEN BIN = 0 ELSE00000000 WHEN BIN = 0 ELSE 00000001 WHEN BIN = 1 ELSE00000001 WHEN BIN = 1 ELSE 00000010 WHEN BIN = 2 ELSE00000010 WHEN BIN = 2 ELSE 00000011 WHEN BIN = 3 ELSE00000011 WHEN BIN = 3 ELSE 00000100 WHEN BIN = 4 ELSE00000100 WHEN BIN = 4 ELSE 00000

55、101 WHEN BIN = 5 ELSE00000101 WHEN BIN = 5 ELSE 00000110 WHEN BIN = 6 ELSE00000110 WHEN BIN = 6 ELSE 00000111 WHEN BIN = 7 ELSE00000111 WHEN BIN = 7 ELSE 00001000 WHEN BIN = 8 ELSE00001000 WHEN BIN = 8 ELSE 00001001 WHEN BIN = 9 ELSE00001001 WHEN BIN = 9 ELSE 00010000 WHEN BIN = 10 ELSE00010000 WHEN

56、 BIN = 10 ELSE 00010001 WHEN BIN = 11 ELSE00010001 WHEN BIN = 11 ELSE 00010010 WHEN BIN = 12 ELSE00010010 WHEN BIN = 12 ELSE 00010011 WHEN BIN = 13 ELSE00010011 WHEN BIN = 13 ELSE 00010100 WHEN BIN = 14 ELSE00010100 WHEN BIN = 14 ELSE 00010101 WHEN BIN = 15 ELSE00010101 WHEN BIN = 15 ELSE 00010110 W

57、HEN BIN = 16 ELSE00010110 WHEN BIN = 16 ELSE 00010111 WHEN BIN = 17 ELSE00010111 WHEN BIN = 17 ELSE 00011000 WHEN BIN = 18 ELSE00011000 WHEN BIN = 18 ELSE 00011001 WHEN BIN = 19 ELSE00011001 WHEN BIN = 19 ELSE 00100000 WHEN BIN = 20 ELSE00100000 WHEN BIN = 20 ELSE 00100001 WHEN BIN = 21 ELSE00100001

58、 WHEN BIN = 21 ELSE 00100010 WHEN BIN = 22 ELSE00100010 WHEN BIN = 22 ELSE 00100011 WHEN BIN = 23 ELSE00100011 WHEN BIN = 23 ELSE 00100100 WHEN BIN = 24 ELSE00100100 WHEN BIN = 24 ELSE 00100101 WHEN BIN = 25 ELSE00100101 WHEN BIN = 25 ELSE 00100110 WHEN BIN = 26 ELSE00100110 WHEN BIN = 26 ELSE 00100

59、111 WHEN BIN = 27 ELSE00100111 WHEN BIN = 27 ELSE 00101000 WHEN BIN = 28 ELSE00101000 WHEN BIN = 28 ELSE 00101001 WHEN BIN = 29 ELSE00101001 WHEN BIN = 29 ELSE VHDL程序設計數字電子表32 00110000 WHEN BIN = 30 ELSE00110000 WHEN BIN = 30 ELSE 00110001 WHEN BIN = 31 ELSE00110001 WHEN BIN = 31 ELSE 00110010 WHEN

60、BIN = 32 ELSE00110010 WHEN BIN = 32 ELSE 00110011 WHEN BIN = 33 ELSE00110011 WHEN BIN = 33 ELSE 00110100 WHEN BIN = 34 ELSE00110100 WHEN BIN = 34 ELSE 00110101 WHEN BIN = 35 ELSE00110101 WHEN BIN = 35 ELSE 00110110 WHEN BIN = 36 ELSE00110110 WHEN BIN = 36 ELSE 00110111 WHEN BIN = 37 ELSE00110111 WHE