ZYNQ平臺架構及配置目錄一、ZYNQ平臺的硬件架構二、AXI協議三、ZYNQ的局部可重構配置ZYNQ平臺的硬件架構背景簡介背景簡介ZYNQ7000系列ARM+FPGA結構XILINX傳統FPGA的局限性？ZYNQ平臺的硬件架構架構：1、PS〔處理器系統〕〔流程控制等串行設計〕2、PL〔可編程邏輯〕〔并行算法設計〕ZYNQ平臺的硬件架構PS由四塊組成：1、APU(應用處理單元)2、內存接口3、IO外設〔USB2.0、Ethernet、CAN、SPI、UART、IIC、SD/SDIO、GPIO〕4、互連線〔APU、IOP和內存單元相互連接，并通過一個多層的AXI互連線與PL連接〕ZYNQ平臺的硬件架構APU結構1、ACP2、SCU3、Cortex-A9(x2)4、L132KB〔I/D〕共享L2512KBZYNQ平臺的硬件架構內存接口ZYNQ平臺的硬件架構IO外設RGMII接口ZYNQ平臺的硬件架構AXI總線架構AXI_HP用于PL的四個高性能、高帶寬主接口，位寬可配64/32，可訪問PS的DDR3控制器和PS的片上RAM資源AXI_GP四個通用接口〔兩主兩從〕，每個位寬32，可訪問PS的DDR3控制器，PS片上RAM資源和其他從設備AXI_ACP用于PL的一個加速一致性主端口，提供快速訪問CPU，可選的L1或L2緩存一致性ZYNQ平臺的硬件架構PL組成：1、可配置邏輯塊(CLB)2、36KB塊BRAM3、數字信號處理DSP48E1Slice4、可編程IO5、時鐘管理6、XADCZYNQ平臺的硬件架構可編程IOZYNQ平臺的硬件架構XADC模塊XADC模塊ZYNQ平臺的硬件架構ZYNQ平臺的硬件架構AXI協議

AXI4.0是ARM公司提出的AMBA3.0協議的升級版，是一種高性能、高帶寬、低延遲的片內總線。AXI協議

AXI協議具有如下特點：總線的地址/控制和數據通道是別離的；支持不對齊的數據傳輸；在突發傳輸中，只需要首地址；同時具有別離讀/寫數據通道；更加容易進行時序收斂。通道介紹AXI接口具有5個獨立通道：寫地址通道〔Writeaddresschannel，AW〕；寫數據通道〔Writedatachannel，W〕；寫響應通道〔Writeresponsechannel，B〕；讀地址通道〔Readaddresschannel，AR〕；讀數據通道〔Readdatachannel，R〕；每個通道都是一個獨立的AXI握手協議。READY/VALID握制每個通道都有一對VALID/READY信號發送方用VALID指示什么時候數據或控制信息是有效的；接收方用READY指示可以接收數據或控制信息。傳輸發生在VALID和READY信號同時為高的時候。通道之間的關系：各個通道都可以獨立握手，相互之間的關系是靈活的；讀數據必須總是跟在與其數據相關聯的地址之后；寫響應必須總是跟在與其相關聯的寫交易的最后出現。READY/VALID握制讀交易中的握手之間的依賴關系寫交易中的握手之間的依賴關系讀交易過程寫交易過程讀猝發交易讀猝發交易過程中典型信號的交互過程寫猝發交易寫猝發交易過程中典型信號的交互過程重疊猝發交易重疊猝發交易過程中典型信號的交互過程AXI互聯AXI互聯結構模型包括：直通模式只轉換模式N-1互聯模式1-N互聯模式N-M互聯模式互聯模式直通模式只轉換模式N-1互聯模式1-N互聯模式N-M互聯模式共享寫和讀地址仲裁結構N-M互聯模式稀疏互聯寫和讀數據通道PartialReconfigurationinZynqBasedonmodulesBasedondiversitiesPartialReconfigurationinZynqWhatProblemsDoesItSolve?Systemcost,size,andpowerconstraints?MultiplexhardwarefunctionsEvolvingprotocolandindustrystandards?ReprogramabilityasstandardsevolveMissioncriticaluptime?UpdateontheflywhilesystemstillrunningLongdesignimplementationcycletimes?AcceleratedevelopmentwithfocusonreconfigurablepartitionSomeTerminologyReconfigurablePartition(RP)

ThephysicallocationofFPGAresourcesselectedforpartialreconfigurationStaticlogicEverythingbuttheRP(s)Thepartofthedesignthatdoesn’tchangeReconfigurableModule(RM)

LogicthatlivesintheRP

?Definedbyhardwareinterfacesandports?FunctionalvariantsforassociatedRP?Differentprotocol,task,filter,etc.DesignFlowStructurethedesign?Separatefunctionsintohierarchicalblocks?Identifyfunctionstobemadeintopartitions?IdentifysetofsignalsthatwillbecomeRPinterfaceDesignFlow?Synthesize?Bottom-up?Static“top”andRMssynthesizedseperatelyDesignFlowAssemblestaticdesignwithRMvariants?RMsreplaceblackboxesinstatic“top”DesignFlowFloorplantheRPsandrunDRCs?Defineregionsandlogicresourcestobe

includedDesignFlowImplementation?Configurationsforstaticlogicandallreconfigurablemodules?RepeatforallmodulesDesignFlowVerifyallconfigurations?EnsurethatstaticportionsmatchidenticallyDesignConsiderationsVivadostoresdesigndataincheckpoints?Savefulldesignasaconfigurationcheckpointforbitstreamcreation?RMscanalsobestoredastheirowncheckpoints?Savestatic-onlycheckpointtobereusedacrossmultipleconfigurations?Routedstaticcheckpointcanremainopeninmemory

?ResultsarelockedattheroutinglevelDesignConsiderationsDesignConsiderationsPartitionPinsarejunctionsbetweenstaticandreconfiguredlogic?Interfacewirescanbebrokenatinterconnect

tilesite?Anchormid-routebetweenstaticand

reconfigurablelogic?Nooverheadatreconfigurablepartition

interfaceDesignConsiderationsNotEverythingCanBeReco