Unit4VLSI設計方法Chap10邏輯綜合與時序仿真Unit4VLSI設計方法Chap10邏輯綜合與1Unit1緒論

Unit2CMOS電路設計基礎

Unit3CMOS電路的邏輯設計

Unit4VLSI設計方法

Chap8設計模式和設計流程

Chap9RTL設計與仿真

Chap10邏輯綜合與時序仿真

Chap11可測試性設計與ATPG

Chap12版圖設計與驗證

Unit1緒論

Unit2CMOS電路設計基礎

2SpecificationExecutablemodelRTLcodeGate-levelnetlistCell/interconnectlevelpositionMask-levelgeometrySystem(Behavioral)levelRTLGate(Logic)levelLayout(Physical)Level設計階段（設計抽象層）設計結果SpecificationSystem(Behaviora3LogicDesign&Simulation:

fromRTL,theninGate-LevelLogicSynthesis得到用已有的基本邏輯單元（庫單元）互聯并滿足一定邏輯功能的邏輯構成Gate-LevelSimulation（門級功能仿真與動態時序分析）一般不做這一步FormalVerification（形式驗證）STA（StaticTimingAnalysis，靜態時序分析）LogicDesign&Simulation:

4HDLCodingforSynthesis

BasedonSynopsysDesignCompilerHDLCodingforSynthesis

Base5

TheImportanceofQualityofSourceCode

Codesthatarefunctionallyequivalent,butcodeddifferentlywillgivedifferentsynthesisresults.YoucannotrelysolelyonDesignCompilerto“fix”apoorlycodeddesign!Trytounderstandthe“hardware”youaredescribing,togiveDCthebestpossiblestartingpoint.

TheImportanceofQualityof6

ThinkHardware!

WriteHDLhardwaredescriptionsThinkofthetopologyimpliedbythecodeDonotwriteHDLsimulationmodelsNoexplicitdelaysNofileI/O

ThinkHardware!

WriteHDLh7

ThinkSynchronous!

Synchronousdesignsrunsmoothlythroughsynthesis,simulation,test,andlayout

Asynchronousdesignsmayrequirehandinstantiationandextensivesimulationtoverify

Isolateasynchronouslogicintoseparatelycompiledblocks

ThinkSynchronous!

Synchron8

ThinkRTL!

WritinginanRTLcodingstylemeansdescribing:

thecircuittopologytheregisterplacementthefunctionalitybetweenregistersDCoptimizeslogicbetweenregisters:

Itdoesnotoptimizetheregisterplacement

ThinkRTL!

WritinginanRT9

SynthesisofifStatements(1)

Theif-elseconstructimpliesmultiplexinghardwareActualcircuitimplementationdependsontargetlibraryandConstraints

SynthesisofifStatements(1)10

SynthesisofifStatements(2)

Toinferlatches,usean‘if’statementwithoutan‘else’clause

SynthesisofifStatements(2)11

SynthesisofcaseStatements

implyparallelmuxfunction

SynthesisofcaseStatements

12SynthesisofFlip-FlopsSynthesisofFlip-Flops13SynthesisofFlip-FlopsSynthesisofFlip-Flops14Synthesis

BasedonSynopsysDesignCompilerSynthesis

BasedonSynopsysD150.IntroductiontoSynthesis1.Pre-SynthesisProcesses2.ConstrainingtheDesign3.SynthesizingtheDesign0.IntroductiontoSynthesis16

WhatIsSynthesis?

Synthesisisthetransformation

ofanideaintoamanufacturabledevicetocarryoutanintendedfunction.在包含眾多結構、功能、性能均已知的邏輯單元電路的目標工藝庫的支持下得到目標工藝庫中單元電路的連接關系（邏輯網絡）的最佳實現方案滿足設計電路的功能要求以及速度、面積等限制條件

WhatIsSynthesis?

Synthesi17

Synthesis’InternalFlow

Synthesis’InternalFlow

18

SynthesisIsConstraint-Driven

SynthesisIsConstraint-Drive19

SynthesisIsPath-Based

SynthesisIsPath-Based

200.IntroductiontoSynthesisPre-SynthesisProcessesTechnologyLibraryforsynthesisDesignHierarchyandPartition2.ConstrainingtheDesign3.SynthesizingtheDesign0.IntroductiontoSynthesis21TechnologyLibrary(1)工藝庫由Foundary提供，一般是.db的格式，這種格式是DC認識的一種內部文件格式，不能由文本方式打開.db格式可以由文本格式.lib轉化過來TechnologyLibrary(1)工藝庫由Foun22

TechnologyLibrary(2)

Duringmapping,DCwill:choose

functionally-correctgatesfromthislibrarycalculatethetimingofthecircuitusingvendor-suppliedtimingdataforthesegates

target_libraryisareservedvariableinDC，youshouldsetittopointtotheTechnologylibraryfile(s)providedbyyoursiliconvendor

TechnologyLibrary(2)

Du23

DesignHierarchy:

RISC_COREexample

DesignHierarchy:

24

DesignHierarchy(Partitioning)

withinHDLDescription

編寫HDL代碼之前（系統設計階段）都需要系統劃分，根據功能或者其他的原則將一個系統層次化地分成若干個模塊，這些模塊內部再進一步細分成模塊/子模塊Entity(VHDL)andmodule(Verilog)statementsdefinehierarchicalblocks.InferenceofArithmeticCircuits(+,-,*,..)cancreateanewlevelofhierarchy.Process(VHDL)andalways(Verilog)statementsdonotcreatehierarchy

DesignHierarchy(Partitioni25

RepartitioningtoDesignHierarchyforSynthesis

在DC做綜合的過程中，默認的情況下各個模塊的層次關系是保留著的。保留著的層次關系會對DC綜合造成一定的影響，比如在優化的過程中，各個模塊的管腳必須保留，這勢必影響到模塊邊界的優化效果

RepartitioningtoDesignHie26

WhyPartitioning/Repartitioning

PartitioningorRepartitioningisdrivenbymany(oftencompeting)needs:SeparatedistinctfunctionsAchieveworkablesizeandcomplexityManageprojectinteamenvironmentDesignReuseMeetphysicalconstraintsAndmany,manyothers

WhyPartitioning/Repartitio27PoorPartitioning:

soShouldEliminateUnnecessaryHierarchy

PoorPartitioning:

28GoodPartitioning(1):

NoHierarchyinCombinationalPaths

GoodPartitioning(1):

29GoodPartitioning(2):

NoHierarchyinCombinationalPaths

GoodPartitioning(2):

30GoodPartitioning(3):

PartitionatRegisterBoundariesGoodPartitioning(3):

31Example(1):AvoidGlueLogicExample(1):AvoidGlueLogic32Example(2):RemoveGlueLogic

BetweenBlocksExample(2):RemoveGlueLogic33BalanceBlockSizeinPartitioning(1)BalanceBlockSizeinPartitio34BalanceBlockSizeinPartitioning(2)BalanceBlockSizeinPartitio35

Top-LevelDesignPartitioning

Top-LevelDesignPartitioning36

Repartitioningwithin

DesignCompiler

Thegroupandungroupcommandsmodifythepartitionsinadesign.Groupcreatesanewhierarchicalblock.Ungroupremoveseitheroneoralllevelsofhierarchy.

Repartitioningwithin

Design37GroupGroup38UngroupUngroup390.IntroductiontoSynthesis1.Pre-SynthesisProcesses2.ConstrainingtheDesignAreaConstraintsTimingConstraintsandTimeBudgetingEnvironmentalAttributesClockConstraints3.SynthesizingtheDesign0.IntroductiontoSynthesis40

SpecifyingAreaConstraints

施加了一個最大面積100單位的約束Unitsarethoseoftargetlibrary,definedbythevendor:2-input-NAND-gatetransistorssquaremils

SpecifyingAreaConstraints

41SpecifyTiming

Constraints(1)SynchronousDesigns:DataarrivesfromaclockeddeviceDatagoestoaclockeddeviceObjective:Definethetimingconstraintsforallpathswithinadesign:1.Theinternal(registertoregister)paths2.Allinputpaths3.Alloutputpaths

SpecifyTimingConstraints(1)42SpecifyTiming

Constraints(2)1.Creatingaclockconstrainstimingpathsbetweenregisterscreate_clock-period10[get_portsClk]SpecifyTimingConstraints(2)43SpecifyTiming

Constraints(3)

2.ConstrainingtheInputPaths

set_input_delay–max(inputdelay)–clockClk[get_portsClk]SpecifyTimingConstraints(3)44SpecifyTiming

Constraints(4)

3.ConstrainingOutputPathsset_output_delay–max(outputdelay)–clockClk[get_portsClk]SpecifyTimingConstraints(4)45

TimeBudgeting(1)

Whatifyoudonotknowthedelaysonyourinputsorthesetuprequirementsofyouroutputs?

CreateaTimeBudget!

TimeBudgeting(1)

Whatify46TimeBudgeting(2)TimeBudgetingTimeBudgeting(2)TimeBudgeti47TimeBudgeting:ExampleTimeBudgetingforMY_BLOCKTimeBudgetingforX_BLOCKandY_BLOCK

TimeBudgeting(3)TimeBudgeting:ExampleTimeB48

ConstrainingforTiming:

WhatIsMissing?

輸入輸出的電平轉換時間(transitiontime)由輸入外圍電路的驅動能力和輸出外圍電路的負載大小決定電路內部的互連線時延的估計當外界溫度或者電路供電電壓發生變化時，時延會相應的改變

ConstrainingforTiming:

Wha49EnvironmentalAttributes(1)set_driving_cell:InputDriveStrengthEnvironmentalAttributes(1)se50EnvironmentalAttributes(2)set_load:OutputCapacitiveLoad

EnvironmentalAttributes(2)se51EnvironmentalAttributes(3)set_wire_load_model:

NetDelaysAWireLoadModel(WLM)isanestimateofanet’sRCparasiticsbasedonthenet’sfanout:ModeliscreatedbyyourvendorEstimatesarebasedonstatisticsfromotherdesignsthevendorhasfabricatedusingthisprocessSpecifyingWLMinDesignCompilerEnvironmentalAttributes(3)se52

EnvironmentalAttributes(4)

OperatingConditionsWhy?Librarycellsareusuallycharacterizedusing“nominal”voltageandtemperature.Ifnot…What?Vendorsallowforsynthesisofcircuitswhichwillnotoperateunder“nominal”conditionsbyembeddingotheroperatingconditionsinthetechnologylibraries

vendor-suppliedoperatingconditions(vendorsmightdelivermultipletechnologylibraries)

EnvironmentalAttributes(4)53OperatingConditions

Tosetoperatingconditions,enterset_operating_conditionscommandDuringsynthesis,“nominal”cellandwiredelayswillbescaledbasedontheoperatingconditionsOperatingConditions54ClockConstraints(1)

RecallTimingConstraintsClockConstraints(1)RecallT55ClockConstraints(2)

對時鐘網絡進行綜合時，需要在時鐘的各條路徑上要插入大小不一的buffer，目的是為了保證時鐘到達每個觸發器的時延盡量相等在定義時鐘之后，都要給該時鐘設置dont_touch，告訴DC不要對時鐘網絡進行綜合（插入Buffer）。這是因為綜合時鐘網絡需要考慮單元的實際物理位置，這是前端的邏輯綜合（DC）不能完成的工作ClockConstraints(2)對時鐘網絡進行綜56ClockConstraints(3)ModelingClockSkew雖然DC無法最終綜合時鐘樹，但是可以加入一些約束讓此時的時鐘更加接近實際的工作情況實際的時鐘達到各個觸發器的時間不是一樣的，它們之間的偏差稱為時鐘偏差(ClockSkew)。為了反映這個偏差，我們在綜合時可以用一個命令來模擬它ClockConstraints(3)Modeling57ClockConstraints(4)ModelingSourceLatency

Clock到達模塊的端口后，要到達內部的觸發器，也要經過一定的延時，這個延時稱為NetworkLatencyClockConstraints(4)Modeling580.IntroductiontoSynthesis1.Pre-SynthesisProcesses2.ConstrainingtheDesign3.SynthesizingtheDesignMultipleInstancesHowtoCompileaHierarchicalDesignTimingAnalysisandReport0.IntroductiontoSynthesis59MultipleInstances(1)DesignsInstantiatedMoreThanOnceuniquifycompile+dont_touchMultipleInstances(1)Designs60MultipleInstances(2)uniquifyvs.compile+dont_touchcompile+dont_touch由于只需對多次例化的模塊編譯一次，可以減少整個設計的編譯時間，減少內存的使用量。在多次例化的模塊很復雜并且工作站硬件條件有限的情況下，其優越性比較明顯。如果這個Ades是一個第三方提供的IP硬核(hard-core)，那么也只能使用這種方法在編譯頂層模塊時，由于Ades設置了dont_touch，這就妨礙了DC針對Ades的各個實例周圍環境的不同的進一步優化，從而使得結果不能真實反映各個實例周圍的環境變化Uniquify由于把各個多例化模塊作為獨立的模塊來看，因此DC可以分別針對它們作出更好的優化，從而得到的結果比較理想編譯的時間稍微較長，但是對于一些不大的模塊來說，這些是可以忽略的。一般推薦使用uniquify解決多例化模塊的綜合問題。MultipleInstances(2)uniquify61CompilingaHierarchicalDesign(1)對一個大型設計來講，有兩種層次化編譯技術自上而下(Top-down)將整個設計一次性讀入，施加頂層約束后直接進行編譯無需考慮各個模塊/子模塊之間的依賴關系，也就不需要制模塊/子模塊之間的時序預算和負載預算，都由DC自動考慮編寫腳本變得簡單，維護起來也比較方便自下而上(Bottom-up)先單獨編譯各個模塊/子模塊：在編譯要考慮與其它模塊之間的關系，給它們加入時序預算和負載預算，看是否滿足約束再讀入頂層文件，施加頂層約束，將各個模塊/子模塊整合起來：頂層編譯完成后還必須看頂層約束是否滿足CompilingaHierarchicalDesig62CompilingaHierarchicalDesign(2)Pros&ConsofBottom-UpCompile

優點利用”分而治之”的策略，對于大型的不可能一次編譯的設計十分有用擺脫了Top-down方法的對工作站硬件條件的限制，使得大型設計也能在一般的機器上編譯完成

缺點實現步驟比較多，尤其對各個模塊之間的時序和負載預算要求很高SummaryCompilingaHierarchicalDesig63TimingAnalysisandReport(1)WhatTooltoUse?DesignCompilerhasabuilt-instatictiminganalyzercalledDesignTimeTimingAnalysisandReport(1)64TimingAnalysisandReport

(2)

DesignTimeTimingReportsTimingAnalysisandReport(2)65LogicDesign&Simulation:

fromRTL,theninGate-LevelLogicSynthesis得到用已有的基本邏輯單元（庫單元）互聯并滿足一定邏輯功能的邏輯構成Gate-LevelSimulation（門級功能仿真與動態時序分析）一般不做這一步FormalVerification（形式驗證）STA（StaticTimingAnalysis，靜態時序分析）LogicDesign&Simulation:

66STA

BasedonSynopsysPrimeTimeSTA

BasedonSynopsysPrimeT67WhatisStaticTimingAnalysis?StaticTimingAnalysis（STA）determinesifacircuitmeetstimingconstraintswithoutdynamicsimulation

Threemainsteps:

DesignisbrokendownintosetsoftimingpathsThedelayofeachpathiscalculatedAllpathdelaysarecheckedtoseeiftimingconstraintshavebeenmetWhatisStaticTimingAnalysis68STAStep1:TimingPathsSTAStep1:TimingPaths69Step1實際是將邏輯電路網表轉換成拓撲圖，圖中的節點(node)代表電路中的引腳(pin)，節點之間的邊