基于FPGA開發板的實201313/1是利用FPGA模塊實現對邏輯門電路的調試。隊員在實驗的過程中，不僅學習了（HardwareDescriptionLanguage，硬件描述語言）ISEFPGA板子的結驗，8255FPGA板子，大家都花費LEDLED燈，并且作FPGA模擬設置基礎硬件，實現馮-諾依曼架構計算機基（3）8255實驗：通過FPGA強大的功能實現了8255并行通訊，并且結合8255的設計 實驗 FPGALED的功能。/LED（3）8255

RS232模塊做串口通訊；8255模塊為我們模擬的主要其中數據處理模塊擔負一切數據處理工作，他處理進入的數據，包括RS232的通訊數CPU寫端口來改變對總線模塊上的優先級進行編程，CPU每次輸BUG，同時也易于對比本次實驗所用XC3S50是Spartan3A系列中最的一款，總共50k邏輯門，70411KB，兩個數字時鐘管理單元，364個差分輸出端口。MicroblazeDW8051軟核，發現邏輯資源IOXC3S200就可以滿足要求；但是基本可以滿足實驗的需求，而且輕量化的方便資源的分配，同時也避免了大面積造成的電路不穩定問題。80C51用用。總線的物理層為標準的雙絞線和DB9接頭RS232DB25接口，IBMPCRS-232DB9連接器，后來成為事實標準，DB25反而沒有什么人應用了。現在絕大多數筆記本電腦上已經不再配備DB9串口接頭，所以采用PL2303將串口轉換USBUART功能。（1）CPUCPU18.432MHzCPU內部的軟件上做改變。其實對于前兩個實（2）8255CPU根據定義，825588D0～D782553個A、B、CA、B、C口及控制寄存器，故地址線為兩根DBD0～D78255CPU8根據定義，82553A、B、C8825524（2）BPB0～PB782558（3）C口：編號為PC0～PC782558LEDLED8段共陰數碼管，所以對應字符的每筆畫端口拉高電平的時候，該筆畫點1234567890對應輸出端UART9600bit/s1120UCLK時鐘周期。188個時鐘周期，則認為起始以后，TXD端口要保持高電平，這樣接收方才可以順暢的接收到發送的數據。LED模塊的輸出。HDL完成設計文件，然后由計算機自動地完成邏輯編譯、化簡、分割、綜合、優化、eda軟件進行設計時需要對其內部原verilogise為基礎進行介紹hdlverilog寫的程序實際上是寫的一段實實在在edahdlverilog語言編好程序后，整個設計的基礎算是打好了，在進行下一步邏輯綜合之multisimeda軟件ise只要在源文件的基礎上再生成一個測試文件就可以進行仿真了。以下是仿真界面師只給出了功能描述，卻沒給出布線圖，于是最后作出來的電路都是五花八門的。eda軟件都要通過這一ise綜合后得到的（rtl級模型（ise中，步驟會對選定的器件進行最終的配置，優化，布局布線，并產生可以到fpga中ise中這兩個功能被包含在了一起eda軟件的不同而有差異，但是對于以上eda適應起來也會相當快的。可編程輸入/輸出單元簡稱I/O單元，是與外界電路的接口部分，完成不氣特性下對輸入2-4FPGAI/O按組分類，物理特性，可以調整驅動電流的大小，可以改變上、下拉電阻。目前，I/O口的頻率也越來FPGADDR2Gbps的數據速率。FPGA了。BIOSParallelPortEPP+ECP（增強型并口）模2ISECPU111CPU和中斷控制器之間的聯絡線，CPU確實已經接1CPUNCPU需要的一系列寄存器，包括中斷NNNNRNRIT_aa這里面包含了對應中斷的中斷號，或者中斷向量N根據大小N應位置1.CPU和控制器約定好的。XilinxIDE漂亮和仿真方便（ISIM，雖然沒有強大但是足夠了畢竟就是看看波形之外和QuartusII比沒有任何優勢。另外，XC3S50slice704個，blockRAM4KBAltera同級別的颶風系列可以說性能上完全被秒殺就連Microblaze都沒法運行導致XilinxSDKverilogC代碼好一點，Verilog語言進行開發，當然就算是VHDL，其實區別也不是很大。關于這塊板子的串口收發問題：直接接好的DB9接頭無論如何都沒有現象，而非直接接Verilog語法及使用方法，初步Verilog的初步應用。正是老師，助教同學對我的幫助，才能讓我順利完成實驗。八.附8255moduleinputoutputwireregregselect_flag,write_flag,read_flag;reg[7:0]out_buf_1;reg[7:0]reg[7:0]reg[7:0]reg[5:0]clk_cout;regclk_range;wireclk_internal;reg[5:0]cout_wr;reg[5:0]reg[5:0]reg[5:0]reg[5:0]reg[5:0]cout_in_num;regin_wire_busy;regin_wire_buf;regin_sample;reg[7:0]core_buf;regregout_wire_busy;regout_sample;reg[5:0]assignclk_internal=clk_range;assignin_buf=in_serial;always(posedgeclkorposedgerst)

always@(posedgecs)always@(posedgewr)always@(posedgerd)always@(posedgeclk_internalorposedgerst)

if(!in_wire_busy&!in_wire_buf)elseif(cout==2)if(cout_in_num>0&&cout_in_num<9)elseif(cout_in_num==9)

elseelseif(cout_out==2)

8255

`timescale1ns///////Create 15:04:15//Design//Module //Project//Tool////////Revision0.01-File//Additionalmoduletop(///////////////Portdeclarations/////////////////////inputgclk;inputrst;input[7:0]sw;inputwr,rd;output[7:0]output[7:0]led2;outputint_btn;input[3:0]inout[7:0]wire[7:0]data_8255;wirecs_n,wr_n,rd_n,a1,a0,cs_8255,cs_button,cs_led1,cs_led2,rst_n;wire[7:0]pa;wire[7:0]wire[3:0]wire[3:0]wire[7:0]wire[7:0]wire[7:0]assigncs_8255=(addr_bus[2]&&!addr_bus[3])?1:0;assigna0=addr_bus[0];assignassigncs_led1=(addr_bus[3]&&!addr_bus[2]&&!addr_bus[1]&&!addr_bus[0])?1:0;assigncs_led2=(addr_bus[3]&&!addr_bus[2]&&!addr_bus[1]&&addr_bus[0])?1:0;assigncs_button=(addr_bus[3]&&!addr_bus[2]&&addr_bus[1]&&!addr_bus[0])?1:0;assignwr_n=~wr;assignrd_n=~rd;assignled1_in=pa;assignassignpch=sw_out[7:4];assignpcl=sw_out[3:0];assignrst_n=~rst;assigncs_n=~cs_8255;assigndata_bus=(!wr&&rd)?data_8255:8'hzz;assigndata_8255=(wr&&!rd)?top_8255top_8255(.cs_n(cs_n),.a1(a1),.a0(a0),_btn(int_btn),ledled module //reset //chipselect //writesignal //readsignal//datainput//controlCport//controlBport//controlAport//dataoutput inputfrominput//inputinput[7:0]d_inbuf,a_inbuf,b_inbuf;input[3:0]c_inbuf_high,c_inbuf_low;//outputcontroloutputreg//outputoutputreg[7:0]d_outbuf,a_outbuf,b_outbuf;outputreg[3:0]c_outbuf_high,c_outbuf_low;//internalsignalregcon;always@(posedgeclk,negedgerst_n)begina_port<=b_port<=c_port<=con<=a_mode_io<=b_mode_io<=1;r_w<=1;c_set_rst<=a_outbuf<=8'hff;b_outbuf<=8'hff;c_outbuf_high<=4'hf;c_outbuf_low<=4'hf;d_outbuf<=8'hff;else//A1.A0.csif(!cs_n)2'b00:2'b01:begin2'b10:begin2'b11:begin

elser_w<=(wr_n&&!rd_n&&!cs_n)?0:1;//r_w=0,read,r_w=1,write if(d_inbuf[7])begina_mode_io<=d_inbuf[4];

b_mode_io<=d_inbuf[1];c_upper_io<=d_inbuf[3];c_lower_io<=d_inbuf[0];c_set_rst<=0;elsec_set_rst<=//C3'b000:c_outbuf_low[0]<=d_inbuf[0];3'b001:c_outbuf_low[1]<=d_inbuf[0];3'b010:c_outbuf_low[2]<=d_inbuf[0];3'b011:c_outbuf_low[3]<=3'b100:c_outbuf_high[0]<=d_inbuf[0];3'b101:c_outbuf_high[1]<=d_inbuf[0];3'b110:c_outbuf_high[2]<=d_inbuf[0];3'b111:c_outbuf_high[3]<=

elsec_set_rst<=//Aif(a_port&&!a_mode_io)begina_outbuf<=d_inbuf;//Bif(b_port&&!b_mode_io)beginb_outbuf<=d_inbuf;//Cif(c_port&&!c_upper_io)beginc_outbuf_high<=d_inbuf[7:4];//Cif(c_port&&!c_lower_io)beginc_outbuf_low<=d_inbuf[3:0]; d_outbuf<=//Aif(a_port&&a_mode_io)begind_outbuf<=a_inbuf;//Bif(b_port&&b_mode_io)begind_outbuf<=b_inbuf;//Cif(c_port&&c_upper_io)begind_outbuf[7:4]<=c_inbuf_high;//Cif(c_port&&c_lower_io)begind_outbuf[3:0]<=c_inbuf_low;

`timescale1ns/

//////Create 20:56:25//Design//Module //Project//Tool////////Revision0.01-File//Additionalmoduleled(clk,rst,sw,led_out,cs);inputclk;inputrst;input[7:0]sw;inputcs;output[7:0]reg[7:0]reg[7:0]always@(posedgeclk)begin default:

if(cs)beginled_out<= module

inputclk;inputrst_n;inputcs_n;inputr_w;input[7:0]outputreg[7:0]d_inbuf;inoutwire[7:0]data_bus;//r_w=0,readport;r_w=1,writetoport data_bus=(!r_w)?d_outbuf:8'hzz;always@(posedgeclk,negedgerst_n)begind_inbuf<=elseif(r_w&&!cs_n)begind_inbuf<=data_bus; inputclk,c_port,c_set_rst,c_upper_io,c_lower_io,rst_n;input[3:0]c_outbuf_high,c_outbuf_low;outputreg[3:0]c_inbuf_high,c_inbuf_low;inout[3:0]c_bus_high,c_bus_low;//internalreg[3:0]//assignc_bus_high=(!c_upper_io)?c_out_high://assignc_bus_low=(!c_lower_io)?c_out_low:always@(posedgeclk,negedgerst_n)beginc_out_high<=4'hf;c_out_low<=4'hf;c_inbuf_high<=4'hx;c_inbuf_high<=elsec_out_high<=4'hf;c_inbuf_high<=elsec_out_high<=c_outbuf_high;c_inbuf_high<=4'hx;

c_out_low<=4'hf;c_inbuf_low<=c_bus_low;elsec_out_low<=c_outbuf_low;c_inbuf_low<=4'hx;elsec_inbuf_high<=4'hx;c_inbuf_low<=4'hx;c_out_high<=c_out_low<=

`timescale1ns/

//////Create 15:51:40//Design//Module //Project//Tool////////Revision0.01-File//Additionalmodulebutton(inputclk;input[7:0]sw;inputcs;outputint_btn;output[7:0]regreg[7:0]reg[7:0]sw_number;assignint_btn=int_sig;always@(posedge )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elsebeginint_sig<=0;sw_out<=8'b if(cs)begin`timescale1ns/

//////Create 15:51:40//Design//Module //Project//Tool////////Revision0.01-File//Additionalmodulebutton(inputclk;input[7:0]sw;inputcs;outputint_btn;output[7:0]regreg[7:0]reg[7:0]sw_number;assignint_btn=int_sig;always@(posedge )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elseif(sw==8'b )beginint_sig<=1;sw_out<=8'b elsebeginint_sig<=0;sw_out<=8'b if(cs)begin module

//control

inputclk,rst_n,a_port,a_mode_io;input[7:0]a_outbuf;output[7:0]a_inbuf;reg[7:0]a_inbuf;inout[7:0]a_bus;reg[7:0]a_out;//a-mode-io0 a_bus=(!a_mode_io)?a_out:8'hzz;always@(posedgeclk,negedgerst_n)begina_out<=8'hff;a_inbuf<=8'hxx;elsea_inbuf<=a_bus;a_out<=8'hff;elsea_out<=a_outbuf;a_inbuf<=8'hxx;elsea_inbuf<=

`timescale1ns///////Create 15:04:15//Design//Module //Project//Tool////////Revision0.01-File//Additionalmodule///////////////Portdeclarations/////////////////////inputuclk;inputinputuart0_rx;inputwr;inputinput[3:0]outputuart0_tx;outputrx_done;outputinout[7:0]wiretx_enable=1;wirewire[7:0]wireassigncs_uart=(addr_bus[3]&&!addr_bus[2]&&addr_bus[1]&&addr_bus[0])?1:0;assignld_tx_data=(wr&&cs_uart)?1:0;assignuld_rx_data=(rd&&assigndata_bus=(!wr&&rd)?rx_data:8'hzz;assigntx_data=(wr&&uart

.tx_done(tx_done),.rx_done(rx_done)`timescale1ns/

//////Create 15:04:15//Design//Module //Project//Tool////////Revision0.01-File//Additionalmoduletop(///////////////Portdeclarations/////////////////////inputgclk;input[7:0]sw;inputwr,rd;outputinput[3:0]inout[7:0]wire[7:0]sw_out;assigncs_button=(addr_bus[3]&&!addr_bus[2]&&addr_bus[1]&&!addr_bus[0])?1:0;assigndata_bus=(!wr&&rd)?sw_out:8'hzz;_btn(int_btn),`timescale1ns/

//////Create 15:51:40//Design//Module //Project//Tool////////Revision0.01-File//Additionalmodulebutton(inputclk;input[7:0]sw;inputcs;outputint_btn;output[7:0]regreg[7:0]reg[7:0]assignalways@(posedge)beginint_sig<=else)beginint_sig<=else)beginint_sig<=else)beginint_sig<=else)beginint_sig<=else)beginint_sig<=else)beginint_sig<=else)beginint_sig<=

elsebeginint_sig<=0;sw_out<=8'b if(cs)beginsw_number<=sw_out;endLED`timescale1ns///////Create 15:04:15//Design//Module //Project//Tool////////Revision0.01-File//Additionalmoduletop(///////////////Portinputgclk;inputrst;inputwr,rd;output[7:0]output[7:0]input[3:0]inout[7:0]wirecs_led1,cs_led2;wire[7:0]wire[7:0]assigncs_led1=(addr_bus[3]&&!addr_bus[2]&&!addr_bus[1]&&!addr_bus[0])?1:0;assigncs_led2=(addr_bus[3]&&!addr_bus[2]&&!addr_bus[1]&&addr_bus[0])?1:0;assignled1_in=(wr&&!rd)?data_bus:8'hzz;assignled2_in=(wr&&!rd)?ledled`timescale1ns/

//////Create 20:56:25//Design//Module //Project//Tool////////Revision0.01-File//Additionalmoduleled(clk,rst,sw,led_out,cs);inputclk;inputrst;input[7:0]sw;inputcs;output[7:0]reg[7:0]reg[7:0]always@(posedgeclk)begin default: if(cs)beginled_out<=CPU `timescale1ns///////Create 15:04:15//Design//Module //Project//Tool////////Revision0.01-File//Additionalmoduletop(///////////////Portdeclarations/////////////////////inputgclk;inputrst_in;input[3:0]ints;output[3:0]addr_bus;outputrst_out;outputwr;outputinout[7:0]wire[7:0]data_cpu;wire[7:0]assignassigndata_bus=(wr&&!rd)?data_cpu:8'hzz;assigndata_cpu=(!wr&&rd)?cpucpu( `timescale1ns///////Create 01:32:26//Design//Module //Project//Tool////////Revision0.01-File//Additional`defineADDR_8255_PB`defineADDR_8255_PC`defineADDR_LED1`defineADDR_LED2modulecpu(clk,rst_cpu,ints,rst,wr,rd, addr,data);inputclk;inputrst_cpu;input[3:0]ints;outputwr;outputrd;outputoutput[7:0]inout[7:0]data;regwr,rd,rst,cfg_8255;wireint_bank3,int_bank2_1,int_bank2_0,int_bank1; regreg[7:0]outbuf,inbuf;reg[1:0]int_btn_proc;regint_rx_proc;assigndata=(wr&&!rd)?outbuf:8'hzz;assignint_bank1=ints[3];assignint_bank2_1=ints[2];//tx_doneassignint_bank2_0=ints[1];//rx_doneassignint_bank3=ints[0];always@(posedgeclk,posedgerst_cpu)beginrst<=cnt1<=cnt2<=cnt3<=int_btn_proc<=int_rx_proc<=cfg_8255<=elserst<=//processbuttoninterruptif(int_btn_proc!=1)beginint_btn_proc<=2;//processing//readbuttonif(cnt2<10)begincnt2<=cnt2+addr<=`ADDR_BTN;wr<=0;rd<=inbuf<=data;outbuf<=inbuf;elseif(cnt2<20)begincnt2<=cnt2+1;addr<=8'hff;wr<=rd<=//writeelseif(cnt2<30)begincnt2<=cnt2+addr<=`ADDR_LED1;wr<=1;rd<=elseif(cnt2<=40)begincnt2<=cnt2+1;addr<=8'hff;wr<=rd<=//writeuarttoelseif(cnt2<=50)begincnt2<=cnt2+1; )beginoutbuf<=8'h31;end )beginoutbuf<=8'h32;end )beginoutbuf<=8'h34;end )beginoutbuf<=8'h35;end )beginoutbuf<=8'h36;end )beginoutbuf<=8'h37;end )beginelseif(cnt2<=60)begincnt2<=cnt2+1;addr<=`ADDR_UART;wr<=1;rd<=elseif(cnt2<=70)begincnt2<=cnt2+1;addr<=8'hff;wr<=rd<=else

cnt2<=int_btn_proc<=1;//processelseint_btn_proc<=0;//nobuttoninterruptcnt2<=0;//processuartrxinterruptint_rx_proc<=1;//processingcnt3<=cnt3+1;wr<=rd<=addr<=`ADDR_UART;inbuf<=data;outbuf<=else//readif(cnt3<10)begincnt3<=cnt3+1;wr<=0;rd<=addr<=`ADDR_UART;inbuf<=data;outbuf<=elseif(cnt3<20)begincnt3<=cnt3+1;addr<=8'hff;wr<=rd<=//writeelseif(cnt3<30)begincnt3<=cnt3+addr<=`ADDR_UART;wr<=1;rd<=elseif(cnt3<40)begincnt3<=cnt3+1;if(outbuf==8'h31)beginoutbuf<=8'b if(outbuf==8'h32)beginoutbuf<=8'b if(outbuf==8'h33)beginoutbuf<=8'b if(outbuf==8'h34)beginoutbuf<=8'b if(outbuf==8'h35)beginoutbuf<=8'b if(outbuf==8'h36)beginoutbuf<=8'b if(outbuf==8'h37)beginoutbuf<=8'b //writeelseif(cnt3<50)begincnt3<=cnt3+addr<=`ADDR_LED2;wr<=1;rd<=elsecnt3<=0;addr<=8'hff;wr<=0;rd<=int_rx_proc<=0;//process

CPU`timescale1ns/

//////Create 15:04:15//Design//Module //Project//Tool////////Revision0.01-File//Additionalmoduletop(///////////////Portdeclarations/////////////////////inputgclk;inputrst_in;input[3:0]ints;output[3:0]addr_bus;outputrst_out;outputwr;outputinout[7:0]wire[7:0]data_cpu;wire[7:0]assignassigndata_bus=(wr&&!rd)?data_cpu:8'hzz;assigndata_cpu=(!wr&&rd)?cpucpu(`timescale1ns/

//////Create 01:32:26//Design//Module //Project//Tool////////Revision0.01-File//Additional`defineADDR_8255_PB`defineADDR_8255_PC`defineADDR_LED1`defineADDR_LED2modulecpu(clk,rst_cpu,ints,rst,wr,rd, addr,data);inputclk;inputrst_cpu;input[3:0]ints;outputwr;outputrd;outputoutput[7:0]inout[7:0]data;regwireint_bank3,int_bank2_1,int_bank2_0,int_bank1; regreg[7:0]outbuf,inbuf;reg[1:0]int_btn_proc;regint_rx_proc;assigndata=(wr&&!rd)?outbuf:8'hzz;assignint_bank1=ints[3];assignint_bank2_1=ints[2];//tx_doneassignint_bank2_0=ints[1];//rx_doneassignint_bank3=ints[0];always@(posedgeclk,posedgerst_cpu)beginrst<=cnt1<=cnt2<=cnt3<=int_btn_proc<=int_rx_proc<=cfg_8255<=elserst<=//configure8255: if(cnt1<10)begincnt1<=cnt1+1;addr<=`ADDR_8255_CFG;outbuf<=8'h89;wr<=rd<=elsecnt1<=0;addr<=8'hff;wr<=0;

rd<=cfg_8255<=//processbuttoninterruptif(int_btn_proc!=1)beginint_btn_proc<=2;//processing//readbuttonif(cnt2<10)begincnt2<=cnt2+addr<=elseif(cnt2<20)begincnt2<=cnt2+addr<=`ADDR_8255_PC;wr<=0;rd<=inbuf<=data;outbuf<=inbuf;elseif(cnt2<30)begincnt2<=cnt2+1;addr<=8'hff;wr<=rd<=//write8255PORTAelseif(cnt2<cnt2<=cnt2+addr<=`ADDR_8255_PA;wr<=1;rd<=elseif(cnt2<50)begincnt2<=cnt2+addr<=`ADDR_LED1;wr<=0;rd<=elseif(cnt2<=60)begincnt2<=cnt2+1;addr<=8'hff;wr<=rd<=//writeuarttoelseif(cnt2<=70)begincnt2<=cnt2+1; )beginoutbuf<=8'h31;end )beginoutbuf<=8'h32;end )beginoutbuf<=8'h33;end )beginoutbuf<=8'h34;end )beginoutbuf<=8'h35;end )beginoutbuf<=8'h36;end )beginoutbuf<=8'h37;end )beginelseif(cnt2<=80)begincnt2<=cnt2+1;addr<=`ADDR_UART;wr<=1;rd<=elseif(cnt2<=90)begincnt2<=cnt2+1;addr<=8'hff;wr<=rd<=elsecnt2<=int_btn_proc<=1;//process

elseint_btn_proc<=0;//nobuttoninterruptcnt2<=0;//processuartrxinterruptint_rx_proc<=1;//processingcnt3<=cnt3+1;wr<=rd<=

addr<=`ADDR_UART;inbuf<=data;outbuf<=else//readif(cnt3<10)begincnt3<=cnt3+1;wr<=0;rd<=addr<=`ADDR_UART;inbuf<=data;outbuf<=elseif(cnt3<20)begincnt3<=cnt3+1;addr<=8'hff;wr<=rd<=//writeelseif(cnt3<30)begincnt3<=cnt3+addr<=`ADDR_UART;wr<=1;rd<=elseif(cnt3<40)begincnt3<=cnt3+1;addr<=8'hff;wr<=rd<=//writeelseif(cnt3<50)begincnt3<=cnt3+addr<=`ADDR_8255_PB;wr<=1;rd<=elseif(cnt3<60)begincnt3<=cnt3+if(outbuf==8'h31)beginoutbuf<=8'b

if(outbuf==8'h33)beginoutbuf<=8'b if(outbuf==8'h34)beginoutbuf<=8'b if(outbuf==8'h35)beginoutbuf<=8'b if(outbuf==8'h36)beginoutbuf<=8'b if(outbuf==8'h37)beginoutbuf<=8'b elseif(cnt3<70)begincnt3<=cnt3+addr<=`ADDR_LED2;wr<=0;rd<=elsecnt3<=0;addr<=8'hff;wr<=0;rd<=int_rx_proc<=0;//process

`timescale1ns/

//////Create 15:57:38//Design//Module //Project//Tool////////Revision0.01-File//Additionalinputdata_in,clk,rst,in_enable,rx_in,uclk,uart_sign;outputdata_out,address_out,enable,tx_out;wire[7:0]data_in;wireclk;wirewirein_enable;wirerx_in;wireuart_sign;reg[7:0]reg[7:0]address_out;regenable;reg[7:0]wire[7:0]reg[7:0]reg[7:0]wireuld_rx_data;wireld_rx_data;wiretx_done;wirerx_done;wiretx_enable;wirerx_enable;reg[7:0]reg[31:0]cout;regrx_load_flag;regtx_load_flag;regtx_flag;regalways@(posedgealways@(posedgetx_done)assignuld_rx_data=rx_load_flag;assignld_tx_data=tx_load_flag;assignrx_enable=rx_flag;assignalways@(posedgeclkorposedgerst)elseif(rx_buf<temp) : : : : : : : :data_out<=8'h07;default:data_out<=8'h71;endcase//case

uartuart `timescale1ns///////Create 15:10:24//Design//Module //Project//Tool////////Revision0.01-File//Additionalmoduleuart( //Port [7:0]tx_data output[7:0]rx_data ;;;//Internalreg reg[3:0] reg wire[7:0] ;reg reg[3:0] reg[15:0] regsample;regassignrx_data=(uld_rx_data)?//UARTRXalways@(posedgeclkorposedgereset)if(reset)begin <= <=8'h00;t<=0; <= <= <= <= <=rx_d1<=sample<=0;endelsebeginrx_d1<=//Uloadtherxif(uld_rx_data)//rx_data <=rx_reg;rx_done<=0;//Receivedataonlywhenrxisenabledif(rx_enable)begin//Checkifjustreceivedstartofframeif(!rx_busy&&!rx_d1)begin <=t<= <=rx_done<=//Startofframedetected,Proceedwithrestofdataif(rx_busy)begint t+ t== t<=//Logictosampleatmiddleofdataif( t==960)begin//200sample<=if((rx_d1==1)&&( t==0))beginrx_busy<=0;rx_done<=0;endelset t+1;rx_done<=//Startstoringtherxif( t>0&& t<9)begin t-1]<=rx_d1;if( t==9)beginrx_busy<=0;//CheckifEndofframereceivedcorrectlyif(rx_d1==0)beginrx_frame_err<=1;endelsebeginrx_done<=rx_frame_err<=//Chec