Modelsim新手入門仿真教程1．打開modelsim軟件，新建一個library。MMadelSimSE-6410.4FileEdrtView匚ompileFileEdrtView匚ompileNewOpen.**LoadCloseProjectImportExpert?SaveCtrl45FolderSource卜Project-.HelpLibrary.DebugArchive十IReaJtsAnaiysrs□占.SimulateAddProjectTookL劭2.library命名XLixa-yName：LbraryPhysicalName：UEKtGixeIIXLixa-yName：LbraryPhysicalName：UEKtGixeIIjCj匚reate日NewLibraryCreatez；q色州hbr呂rvP"amaptoartxtstirtglibraryP"an已vlibraryandalogicalmappingtcit3.新建一個工程。AleEditViewCompile^imuhteAddProject「口口1$NewFolderOpen.,,Source卜7ba^d卜Prqjed:...J6derseProjectLtrary?.Import?Debug；Archive.PB1LExpert卜ResultsAralvssDatabase,Save匚訊特SaveAs…Report.”f'harin&nirar+rwu*XVQ匚anu凸CopySettingsFrom0,4/exajq:Le5Z^iixielsijnxiniBrowse…|?Cop7LibraryMappings”ReferenceLibraryMapomgsC：/modeltech6410.i/exaicplesL^xarYNameMCreateProjectProjectLocationBrowse^3.出現(xiàn)下面界面，點擊close。4.新建一個verilog文件SimijlateAddProjectTool?LayoutBookmarks譏SimijlateAddProjectTool?LayoutBookmarks譏FileEditViewCompileNewOpen.”TOC\o"1-5"\h\zLoad1CloseProjectImpcrt1Expert1SaveCtrl+SSaveAs…Report...rWi&rty'kruFolderSoltmProject-“Library.,.DebugArdirve...ResuHsAraR銅Database-4.鍵入主程序。下面以二分之一分頻器為例四ihapri-I卑rftjj'C:hv出1站￡4_0^taDMte^IjrlM-Lv-Made■—IE]nMjulthjlf_eLlIEeMr^clt^ia.Elk_MHI?丄護g<s】k_】mi^FC辦]|outpreE]k_CHrE.ri『Egjwt；5|*iw^a9iDh^vdirvclk_i<申bcg-lniIli|!Etam鼻Clt_CIM：*CJ*Iifigip1：elh_3OE"-cli_-3utrr*M:L文件代碼：modulehalf_clk(reset,clk_in,clk_out);inputclk_in,reset;outputclk_out;regclk_out;always@(negedgeclk_in)beginif(!reset)clk_out=0;elseclk_out=~clk_out;endendmodule編輯完成后，點擊保存。EjzlAllCclumnsM亂ikimnLayoutFileEdit^/iewCompileSimulateAddSourceToolsEjzlAllCclumnsM亂ikimnLayoutFileEdit^/iewCompileSimulateAddSourceToolsStatuhyreIOrdeiModified1^1Project^NameMA?保萍在CD樓翌日朝快逹話問CJM35IXC^wincfows.drilgmMA?保萍在CD樓翌日朝快逹話問CJM35IXC^wincfows.drilgmmixedh>ngpsJ■syrtemc巒怯rwerik>gitext203&/7/<11^42020/7/411:042020/7/411^4￡020/7/411KM2D20/7/4112025/7/411^2D20/7/411;042QKJ/7/411:042020/T/411:042020^/723:162020/7/411:04HinTflbrt1FP.M11文件老⑷：W3B性存繪3〔卄：文件名要與module后面的名稱相同。5?再新建一個測試文件，步驟同上面新建的主程序文件，文件名后綴改為.vt程序代碼如下：'timescale1ns/100ps'defineclk_cycle50moduletop;regclk,reset;wireclk_out;always#'clk_cycleclk=~clk;initial

beginclk=0;reset=1;#10reset=0;#110reset=1;#100000$stop;endhalf_clkm0(.reset(reset),.clk_in(clk),.clk_out(clk_out));Endmodule6.添加文件，編譯文件先右鍵點擊左邊空白處，選擇addtoproject—existingFileFileEditSew匸口mpileSirnulat?AddProjectTodsLayufBoDlcmarkiWh-hJctwHelp

畫盂丨x脈爼口二丨莎」料生］|炒|翥］|魯塾幽璘僵”tIftC\/!KdHtKho4_lQ.4^7MT0iM1tl￡_Cyd*s--DtIWjft't^macdle丄n97JQC>R3defic-Ecit_cy€ieMnoduletcprU丄thniretjwirecll_cu￡;iLlviyafelk:_c：^cleMAyI出UnlUilXWC13E-3Jrtser-l"1-10EeseQ-0,!I1J.Qrcwt-1：flOOGCFOiSTcp-tud［^1hBif_cliEfiij選擇剛剛新建的兩個文件。按ctrl鍵可以同時選擇兩個，選擇打開，下一步點擊ok7選中其中一^，右鍵，選擇complieTcomplieall7/20201L1J3I5LCofnpilePropei'bes,,.ProjectSettings,*Na?匚ompileAddtoProjectRemovefi'omPtojectCofnpileOjtof-D&teCloseProjectCompileOrder,nHUpdateCcmpdeReport...PropeitM.匚ompileSurnrnary.r.Stati^TypeOrdsModifieddk_tYde.vtMtExecvtef/07/202011:39:52…con^ileAll出現(xiàn)兩個勾，說明編譯通過。出現(xiàn)x,說明文件編譯出錯，雙擊x,可以查看錯誤。MModelSimSr-6410.4FileEditView匚ompileSimulateAddProjectTool?LayoutB凸ProjectFileEditView匚ompileSimulateAddProjectTool?LayoutB凸Projectdkrl^arne8.終于可以仿真了選擇simulate^startsimulateMModelSimSE-6410.4FileEdrtViewCompile*晉|黃〔ColurnnLayout|a11Co1ueiisHelpMFileEdrtViewCompile*晉|黃〔ColurnnLayout|a11Co1ueiisHelpM③酗X#SimulateAddProjectToolsLayoutBookmarksWindcDesignOptinirzatjori-,.Start5<miJaticn.^RGntMT*eOptions-*.StegRestart...BreakEndSimulation33：51...選擇剛剛新建的庫里面的top,或者測試文件名稱，左下角的enableoptimization—定要去掉勾，有勾的畫不會出來波形，一定要去掉勾！一定要去掉勾！一定要去掉勾！（本人也不清楚原因，都是初學者，嘻嘻）MStartSimuhtioriXDesign]VHDL]Verilog]Libraries]5DF]Others]TNann亡TvcePath+血Yak-■￡text_]half_ckTNann亡TvcePath+血Yak-■￡text_]half_ck”topftoatfixlfcie&e_env(empty)infactncZjib(empty)mgc^ams(empty)mtiAvmLibraryLbraryModuleworkC:/modelte±64_10.4/exarnples/tExtC:/m&deltech64_10.斗足xarnples/half_dk