1、EE141 Digital Integrated Circuits2ndManufacturing1一、CMOS工藝簡介；二、MOS管特性；三、Layout設(shè)計(jì)；四、估算寄生參數(shù)；五、SPICE中 MOS器件參數(shù)設(shè)置 參考書： ， EE141 Digital Integrated Circuits2ndManufacturing2Technology (Process) 三類工藝： 雙極型 bipolar (三極管，二極管，電阻 ) NMOS CMOS （NMOS，PMOS）：目前主流工藝EE141 Digital Integrated Circuits2ndManufacturing3EE1

2、4129 Digital Integrated Circuits2ndIntroductionDie CostDie CostSingle dieWaferFrom http:/Going up to 12” (30cm)EE141 Digital Integrated Circuits2ndManufacturing4q芯片制造代工廠芯片制造代工廠 （Foundry）1 1） TSMC TSMC 臺積電臺積電 （臺灣）（臺灣） 可獲工藝：0.5um, 0.35um, 0.25um, 0.18um, 0.13um, 0.09um 0.065um, 0.045um 2 2） CSM CSM 或稱

3、或稱 Chartered Chartered 新加坡特許新加坡特許 （新加坡）（新加坡） 可獲工藝：0.35um, 0.25um, 0.18um, 0.13um, 0.09um, 0.065um, 0.045um 3 3） SMIC SMIC 中芯國際中芯國際 （上海）（上海） 可獲工藝：可獲工藝：0.350.35um, 0.25um, 0.18um, 0.13um, 0.09umum, 0.25um, 0.18um, 0.13um, 0.09um4 4）HJTCHJTC或稱或稱 HJ HJ 和艦科技和艦科技 ( (蘇州蘇州) ) 可獲工藝：0.35um, 0.25um, 0.18um5 5）

4、CSMC CSMC 華潤上華華潤上華 （無錫）（無錫） 可獲工藝：3.0至0.5微米6 6）GSMC GSMC 宏力宏力 ( (上海上海) ) 可獲工藝：0.25um, 0.18um, 0.15um7 7）HHNEC HHNEC 華虹華虹 ( (上海上海) ) 可獲工藝：0.35um, 0.25um, 0.18um8 8）SinoMOS SinoMOS 中緯中緯 ( (寧波寧波) ) 可獲工藝：0.8um/1umEE141 Digital Integrated Circuits2ndManufacturing5q多項(xiàng)目晶圓服務(wù)多項(xiàng)目晶圓服務(wù) 多項(xiàng)目晶圓（多目標(biāo)芯片） Multi Project

5、 Wafer - MPW多個(gè)使用相同工藝的設(shè)計(jì)，放在同一晶圓片上流片。每個(gè)設(shè)計(jì)可以得到數(shù)十片芯片樣品。制造費(fèi)用按照芯片面積分?jǐn)偅杀緝H為單獨(dú)進(jìn)行制造的5%-10%。 EE141 Digital Integrated Circuits2ndManufacturing6qEducational services （MPW服務(wù)機(jī)構(gòu)）服務(wù)機(jī)構(gòu)） 美國：MOSIS (MOS Implementation Support Project) http:/ 臺灣：CIC (Chip Implementation Center) .tw/cic_v13/main.jsp 歐盟：

6、Europractice http:/ 上海集成電路設(shè)計(jì)研究中心 http:/ 中國科學(xué)院EDA中心 http:/ EE141 Digital Integrated Circuits2ndManufacturing7MOS 管結(jié)構(gòu)圖: 3D PerspectiveDSGGDSDSGEE141 Digital Integrated Circuits2ndManufacturing8substraten+ n+p+substratemetal1polySiO2metal2metal3transistorviametal1insulator.多晶硅（襯底）Cross sectionEE141 Dig

7、ital Integrated Circuits2ndManufacturing9CMOS有三類工藝：EE141 Digital Integrated Circuits2ndManufacturing10EE141 Digital Integrated Circuits2ndManufacturing11p-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2EE141 Digital Integrated Circuits2ndManufacturing12VDDVDDVinVoutM1M2M3M4Vout2EE141 Di

8、gital Integrated Circuits2ndManufacturing13 1） oxidation （氧化）Si-substrate or P-type or N-typeSi-substrate or P-type or N-typeSiO2氧氣SiO2 是絕緣體。是絕緣體。 它的作用是什么？它的作用是什么？EE141 Digital Integrated Circuits2ndManufacturing14SiO2 是絕緣體。是絕緣體。 它的作用是什么？它的作用是什么？EE141 Digital Integrated Circuits2ndManufacturing152）

9、Cut（光刻）(a) Photoresis (光刻膠)PhotoresistSiO2Si-substrate(d) Final result after removal of resist 去膠去膠Si-substrate(b) Exposure 曝光曝光UV-light 紫外光紫外光mask 版圖版圖PhotoresistSiO2(c) Etch 蝕蝕刻chemical etchPhotoresistSiO2EE141 Digital Integrated Circuits2ndManufacturing163） doping（摻雜）五階元素五階元素SIO2起到掩蔽作用起到掩蔽作用N-typ

10、e擴(kuò)散 diffusion離子注入 ionize （現(xiàn)在工藝）EE141 Digital Integrated Circuits2ndManufacturing174） 連線連線：多晶硅 金屬EE141 Digital Integrated Circuits2ndManufacturing18First place tubs to provide properly-doped substrate for n-type, p-type transistors:p-tubn-tubsubstrateP-well （P阱）Process steps 1: 襯底上做阱EE141 Digital Int

11、egrated Circuits2ndManufacturing19Pattern polysilicon before diffusion regions:p-tubn-tubpolypolygate oxideEE141 Digital Integrated Circuits2ndManufacturing20Add diffusions, performing self-masking:p-tubn-tubpolypolyn+n+p+p+EE141 Digital Integrated Circuits2ndManufacturing21Start adding metal layers

12、:p-tubn-tubpolypolyn+n+p+p+metal 1metal 1viasEE141 Digital Integrated Circuits2ndManufacturing22Vgs Vt : 產(chǎn)生反型層Vgs VTN ，VDS VTN ，VDS VGS VTN)1 ()(22DSnTNGSnnOXndVVVLWCI2)(2)(22DSDSTNGSnnoxnDSDSTNGSndVVVVLWCVVVVkIIDoxoxnOXnntCkprocess transconductance工藝跨導(dǎo)工藝跨導(dǎo))(nnOXnnLWCkdevice transconductance器件跨導(dǎo)器件跨導(dǎo)

13、nnChannel-length modulation溝道長度調(diào)制系數(shù)溝道長度調(diào)制系數(shù)carrier mobility 電子遷移率電子遷移率COX - gate capacitance per unit area EE141 Digital Integrated Circuits2ndManufacturing26Vtn = 0.6VVtp = -0.6V)1 ()(22DSnTNGSnnOXndVVVLWCI)1 ()(22SDnTPSGppOXpdVVVLWCIIDIDThreshold voltage （以飽和區(qū)方程為例）：以飽和區(qū)方程為例）：)22(0FSBFnTNTNVVVThres

14、hold voltage for VSB=0)22(0FBSFpTPTPVVV0TNVnFBody-effect coefficientFermi potential (typical 為為 -0.3V)費(fèi)米電勢費(fèi)米電勢Bulk 調(diào)制效應(yīng)，總是使有效閾值電壓的絕對值增大調(diào)制效應(yīng)，總是使有效閾值電壓的絕對值增大一個(gè)例子 : NMOS管的VTN0 =0.68V, 當(dāng)VSB =-5V時(shí)， Vt =0.16V. 有效閾值電壓Vt =Vt0 + Vt=0.84VEE141 Digital Integrated Circuits2ndManufacturing27線性區(qū)線性區(qū)兩端均開啟兩端均開啟截止區(qū)截止

15、區(qū)兩端均不開啟兩端均不開啟飽和區(qū)飽和區(qū)一端開啟；另一端不開啟一端開啟；另一端不開啟（S端開啟；端開啟；D端不開啟）端不開啟）gatedrainsourcecurrentIdgatedrainsourceId源端開啟源端開啟Vgs Vtn漏端開啟漏端開啟Vgd Vtn源端開啟源端開啟Vgs -Vtp漏端開啟漏端開啟Vgd -VtpVtn = 0.6VVtp = -0.6VEE141 Digital Integrated Circuits2ndManufacturing28PolysiliconAluminum1、Layout 基本概念EE141 Digital Integrated Circui

16、ts2ndManufacturing29Masks are tooling for manufacturing 版圖用于做IC.Manufacturing processes have inherent limitations in accuracy 制造工藝有精度限制.Design rules specify geometry of masks which will provide reasonable yields. 版圖設(shè)計(jì)規(guī)則規(guī)定了版圖的幾何形狀、大小等，以獲得合理的成品率.Design rules are determined by experience. 版圖設(shè)計(jì)規(guī)則由實(shí)驗(yàn)決定EE

17、141 Digital Integrated Circuits2ndManufacturing30SCMOS 是MOSIS制定的按比例縮小設(shè)計(jì)規(guī)則：基本采用按比例縮小設(shè)計(jì)規(guī)則，再加上一些限制。 1）Designed to scale across a wide range of technologies. 適用于寬廣的工藝節(jié)點(diǎn) 2）Designed to support multiple vendors. 適用于各種制造商 3）Designed for educational use. 用于教學(xué)目的（為了方便） 4）Therefore, fairly conservative 因此，與理想的按

18、比例縮小設(shè)計(jì)規(guī)則相比，相當(dāng)保守231325EE141 Digital Integrated Circuits2ndManufacturing31LayerPolyMetal1Metal2Contact To PolyContact To DiffusionViaWell (n)Active Area (p+)ColorRepresentationGreenGreenRedBlueMagentaBlackBlackBlackActive Area (n+)Yellowtub ties (p+)tub ties (n+)Well (p)Yellow2、CMOS Process Layers 工藝層

19、定義有源區(qū)(擴(kuò)散層)接觸孔通孔EE141 Digital Integrated Circuits2ndManufacturing32n-type 多晶硅與擴(kuò)散區(qū)的交界處Poly（紅）擴(kuò)散區(qū):綠:：N+黃：P+EE141 Digital Integrated Circuits2ndManufacturing33Poly（紅）擴(kuò)散區(qū):黃：P+（PMOS）擴(kuò)散區(qū):綠:：N+（NMOS）Metel (上方常是電源）Metel (下方常是電源）EE141 Digital Integrated Circuits2ndManufacturing34 aoutaoutVDDVSSMetel (上方常是電源）M

20、etel (下方常是電源）PMOS通常與電源相連(在上方）NMOS通常與地相連(在上方）EE141 Digital Integrated Circuits2ndManufacturing35wL溝道長度溝道寬度電流方向W=擴(kuò)散區(qū)寬度EE141 Digital Integrated Circuits2ndManufacturing36p-tubn-tubpolypolyn+n+p+p+metal 1metal 1柵氧：薄，會(huì)產(chǎn)生反型層場氧：厚，不會(huì)產(chǎn)生反型層EE141 Digital Integrated Circuits2ndManufacturing37 （Scalable Design r

21、ules）：工藝參數(shù)與版圖尺寸按比例縮小 EE141 Digital Integrated Circuits2ndManufacturing381）Intra-Layer Design Rules 層內(nèi)設(shè)計(jì)規(guī)則Polysilicon22Metal133Metal2432Contactor Via2Hole單位： tub tiesN+，P+221090 Well不同阱阱相同阱阱or6ActiveN+，P+3310相同擴(kuò)散層擴(kuò)散層不同擴(kuò)散層擴(kuò)散層EE141 Digital Integrated Circuits2ndManufacturing39最小寬度最小寬度 最小間距最小間距Polysilic

22、on 2 2 metal1 3 3 有源區(qū)（擴(kuò)散區(qū)，有源區(qū)（擴(kuò)散區(qū)，N+，P+） 3 3 Contact or Via Hole 2 2 2Contactor Via2HoleMetal133Polysilicon22ActiveN+，P+33EE141 Digital Integrated Circuits2ndManufacturing402）Inter-Layer Design Rules 層間設(shè)計(jì)規(guī)則單位： Transistors重要231325EE141 Digital Integrated Circuits2ndManufacturing41單位： W 3 最小尺寸最小尺寸L 2P

23、oly伸出有源區(qū) 2擴(kuò)散層伸出poly 3Poly與有源區(qū)間距 12323115擴(kuò)散層與阱邊緣間距 5EE141 Digital Integrated Circuits2ndManufacturing42可獲得的Contact hole and Via hole metal1/diff 接觸孔 metal1/poly 接觸孔 metal1/metal2 通孔 metal2/metal3 通孔4122 通孔尺寸通孔尺寸42122overlap (復(fù)蓋) : 1 diff接觸孔與poly間距： 2 minimum spacing(間距): 2 Cut(通孔): 2 x 2 EE141 Digita

24、l Integrated Circuits2ndManufacturing434122 尺寸尺寸 cut: 2 x 2 overlap : 1 minimum spacing: 2 阱接觸與diff接觸孔間距：2 2P. 81-82EE141 Digital Integrated Circuits2ndManufacturing44AAnp-substrateFieldOxidep+n+InOutGNDVDD(a) Layout(b) Cross-Section along A-AAAEE141 Digital Integrated Circuits2ndManufacturing45EE14

25、1 Digital Integrated Circuits2ndManufacturing46poly_not_fet to all_diff minimum spacing = 0.14 um.EE141 Digital Integrated Circuits2ndManufacturing47+baoutbaoutVDDGNDtubties4、其它單元電路版圖簡介EE141 Digital Integrated Circuits2ndManufacturing48baoutaboutVDDGNDtub tiesEE141 Digital Integrated Circuits2ndManu

26、facturing49inoutRL = ?CL = ?EE141 Digital Integrated Circuits2ndManufacturing50DSGBCGDCGSCSBCDBCGB復(fù)蓋EE141 Digital Integrated Circuits2ndManufacturing51PolysiliconAluminumEE141 Digital Integrated Circuits2ndManufacturing52qResistance of any size square is constant 任何尺寸的方塊，電阻相同R = rH WLSheet Resistanc

27、eR口 = R口 （L / W）WLHnSheet Resistance 方塊電阻R1R2EE141 Digital Integrated Circuits2ndManufacturing53源/漏Parasitic ResistancesWLDDrainDraincontactPolysilicon gateDSGRSRDVGS,effWLRRRDviaD/口viaR口R通孔電阻源/漏擴(kuò)散層方塊電阻WLD/源/漏擴(kuò)散層方塊數(shù) （spice參數(shù)，RSH）EE141 Digital Integrated Circuits2ndManufacturing54 5 20 30 5 20 寄生電阻估算

28、Poly resistivity Rpoly 4 /口 多晶硅方塊電阻線彎角電阻計(jì)算（僅正方形）：0.5方塊EE141 Digital Integrated Circuits2ndManufacturing55Sheet Resistance的典型數(shù)值Metal: 電阻最小多晶硅、N+、P+： 電阻大 （約50倍）各類線電阻比較EE141 Digital Integrated Circuits2ndManufacturing56substrate1） Poly/metal線-襯底電容 Two components （兩部分）: parallel plate （平板電容） Fringe （邊緣電

29、容）.Metal / ployfringeplateEE141 Digital Integrated Circuits2ndManufacturing57DielectricSubstrateLWHtdiElectrical-field linesCurrent flowSCWLtcplatedidi1（1）parallel plate （平板電容）plateC單位面積平板電容S平板面積EE141 Digital Integrated Circuits2ndManufacturing58（2）Fringe （邊緣電容）LCcfringe2SubstrateL邊緣電容2CCC1EE141 Dig

30、ital Integrated Circuits2ndManufacturing59qCan couple to adjacent wires on above/below layers 不同層之間耦合電容 metal 2metal 1metal 1SCcmm32, 12, 1 mmCS單位面積m1與m2耦合電容m1與m2復(fù)蓋面積3cnCan couple to adjacent wires on same layer 同一層之間耦合電容 xlCcmm1, 14 x4cEE141 Digital Integrated Circuits2ndManufacturing603、Diffusion

31、capacitance formed by p-n junctions （P-N結(jié)擴(kuò)散電容）depletion region耗盡層n+ (ND)substrate (NA)bottomwallCapacitance底部電容sidewallCapacitances側(cè)壁電容EE141 Digital Integrated Circuits2ndManufacturing61CJSW= CJSW0 (1 + Vr/Vbi) msw CJSW0 zero-bias sidewall capacitance (零偏壓側(cè)壁電容) （SPICE參數(shù)） msw sidewall grading coeffic

32、ient ( 側(cè)壁電容梯度系數(shù)) （SPICE參數(shù)） 若突變結(jié)（abrupt junction）, msw = - Vr voltage across the junction (P-N 結(jié)反偏電壓) Vbi built-in voltage （ P -N 結(jié)內(nèi)建電勢） Vbi = (k*T/q) ln(NAND/ni2) 1） Sidewall capacitances 側(cè)壁電容n+ (ND)substrate (NA)EE141 Digital Integrated Circuits2ndManufacturing62CJ= CJ0 (1 + Vr/Vbi) m CJ0 zero-bias

33、 bottomwall capacitance (零偏壓底部電容) （SPICE） m bottomwall grading coefficient (底部電容梯度系數(shù)) （SPICE） 若突變結(jié)（abrupt junction）, m = - Vr voltage across the junction (P-N 結(jié)反偏電壓) Vbi built-in voltage （ P -N 結(jié)內(nèi)建電勢） Vbi = (k*T/q) ln(NAND/ni2) 2） bottomwall capacitance 底部電容n+ (ND)substrate (NA)EE141 Digital Integra

34、ted Circuits2ndManufacturing630.12u各類線電容比較Metal: 電容最小多晶硅： 電容也較小N+、P+： 電容大 （十倍以上） EE141 Digital Integrated Circuits2ndManufacturing64各類線電容、電阻比較 線線 電容電容 電阻電阻 線性能線性能 用途用途Metal 最小 最小 好 各類線 多晶硅 較小 大 （約50倍） 中 局部連線N+、P+ 大 （約十倍） 大 （約50倍） 差 MOS管內(nèi)部線（重要）EE141 Digital Integrated Circuits2ndManufacturing65qGate to substrate 柵-襯底電容 CGBqgate to source/drain overlap capacitances 柵源/漏電復(fù)蓋電容 CGS CGDqSou