1、電子設計自動化中英文翻譯 畢業論文附錄B 翻譯原文Electronic design automationKeyword EDA; IC;VHDL language; FPGAPROCESS DESCRIPTION Three obstacles in particular bedevil ic designers in this dawn of the system on a chip. The first is actually a shortfall-the hardware and software components of the design lack a unifying la

2、nguage. Then, as the number of logic gates per chip passes the million marks, verification of a design's correctness is fast becoming more arduous than doing the design itself. And finally, not only gate counts but chip frequencies also are climbing, so that getting a design to meet its timing r

3、equirements without too many design iterations is a receding goal. As is the wont of the electronic design automation (EDA) community, these concerns are being attacked by start-up companies led by a few individuals with big ideas and a little seed money.PARLEZ-VOUS SUPERLOG?A system on a chip compr

4、ises both circuitry and the software that runs on it. Such a device may contain an embedded processor core running a software modem. Most often, after the chip's functionality is spelled out, usually on paper, the hardware com- potent is handed off to the circuit designers and the software is gi

5、ven to the pro- grammars, to meet up again at some later date. The part of the chips functionality that will end up as logic gates and transistors is writ- ten in a hardware design language-Virology or VHDL, while the part that will end up as software is most often described in the programming langu

6、age C or C+. The use of these disparate languages hampers the ability to describe, model, and debug the circuitry of the IC and the software in a coherent fashion.It is time, many in the industry believe, for a new design language that can cope with both hardware and software from the initial design

7、 specification right through to final verification. Just such a new language has been developed by Co-Design Automation Inc., San Jose, Calif. Before launching such an ambitious enterprise, cofounders Simon Davidmann, who is also chief operating officer, and Peter Flake ruled out the usefulness of e

8、xtending an existing language to meet system-on-chip needs. Among the candidates for extension were C, C+, Java, and Verilog. A design language should satisfy three requirements, maintained Davidmann. It should unify the design process. It should make designing more efficient. And it should evolve o

9、ut of an existing methodology. None of the existing approaches filled the bill. So Davidmann and Flake set about developing new co-design language called Superlog. A natural starting point was a blend of Virology and C since "from an algorithm point of view, a lot of Virology is built on C,&quo

10、t; explained Davidmann. Then they spiced the blend with bits and pieces of VHDL and Java. From Virology and VHDL, Superlog has acquired the ability to describe hardware aspects of the design, such as sequential, combinatorial, and multivalued logic. From C and Java it inherits dynamic processes and

11、other software constructs. Even functions like interfaces, protocols, and state machines, which till now have often been done on paper, can be described in the new language. To support legacy code written in a hardware description or programming language, Superlog allows both Virology and C modules

12、to be imported and used directly.It is important for the language to be in the public domain, according to Davidmann. The company has already begun to work with various standards organizations to this end. Not to be overlooked is the need for a suite of design tools based on the language. Recently C

13、o-Design identified a number of electronic design automation companies, among them Magma Design Automation, Sente, and Viewlogic, that will develop tools based on Superlog. Co-Design will also develop products for the front end of the design process.ARACE TO THE FINISH Not everyone is convinced that

14、 a new language is needed. SystemC, a modeling platform that extends the capabilities and advantages of C/C+ into the hardware domain has been proposed as an alternative. Such large and powerful companies as Synopsys, Coware, Lucent Technologies, and Texas Instruments have banded together under the

15、Open SystemC Initiative to promote their version of the next-generation design platform. To get SystemC off to a running start, the group offers a modeling platform for download off their Web site free of charge. Their hope is also to make their platform the de facto standard. The rationale for deve

16、loping SystemC was straightforward, according to Joachim Kunkel, general manager and vice president of the System Level Design Business Unit at Synopsys. It was to have a standard language in which semiconductor vendors, IP vendors, and system houses could exchange system-level IP and executable spe

17、cifications, and the electronic design automation industry could develop interoperable tools. Supporters of SystemC believe that the would-be standard has to be based on C+ because it allows capabilities to be added to it without leaving the language standard, Kunkel told JEEE Spectrum. Most softwar

18、e developers use C+ and many systems developers use C+ already to describe their systems at a behavioral level. But till now it has not been possible to describe hardware using the language.The developers of SystemC have solved that problem by defining new C+ class libraries and a simulation kcrne1

19、that bring to C+ all of the capabilities needed to describe hardware. "These new classes implement new functionality," explained Kunkel. "For example, bit vectors-strings of zeros and ones-and all the operations that you would do on them." The SystemC developers also provided a c

20、lass of signed and unsigned numbers, the notion of a signal, and other concepts needed to model hardware. There are still some holes, however. For example, it is still not possible to synthesize a gate-level netlist from a SystcmC description. Rut synthesis tools for SysteniC would he a natural resu

21、lt of broad acceptance of the language within the user community, according to Kunkel. It remains to be seen whether SystemC or Superlog wins out in the end. Least desirable would be an outcome like the impasse between Virology and VHDL, in which both prevailed, forcing electronic design automation

22、vendors to support both platforms in a wasteful duplication of effort. THE VERIFICATION NIGHTMARE If today's complex ICs are tough to design, they are very much tougher to verify. A variety of tools are available, each with its pros and cons. Emulation translates a design into field-programmable

23、 gate arrays (FPGAs). Presumably, if the array works as planned, the final chip will also. The emulation platform also enables designers to try 0111 the software that will run on the ASIC. The approach, though, is slow. Typical emulation systems run at a few megahertz. "At roughly one million c

24、ycles per second, designers arc not getting cnough performance out of their emulation systems to verify or understand some of the things that are going on with video generation or high bandwidth communications," said John Gallagher, director of marketing for Synplicity Inc., Sunnyvale, Calif. T

25、hey must process a large number of operations to ensure their functionality is correct, he added. The reason that emulation systems are so slow, according to Gallagher, is that they route the design through many FPGAs and many boards. Simplicity solution is to use a few high-end FPGAs having over on

26、e million gates running at 100 MHz. Typically, a million FPGA gates translates into 200 000 ASIC gates. Putting nine such chips on a board in a three-by-three array allows designers to represent up to 1.8million ASlC gates. And routing delays are greatly curtailed because each chip is no more than t

27、wo hops away from any other chip in the array. The company% product, called Certify, is not intended to compete with reconfigurable emulation systems, which are very effective at debugging designs during the internal design process, explained Gallagher. Rather, it is a true prototype of the system,

28、running at speeds that may approach the real thing. Certify handles three fundamental operations, said Gallagher. The first is partitioning, or breakings up the ASIC register transfer level (RTL) code into different FPGAs. It does synthesis, turning the RTL code into ASIC gates equivalent to the fin

29、al ASIC gates. Then it does timing analysis. "We haven't just linked together the different tools,” he explained. 'We have taka our synthesis algorithms, between the partitioning capabilities, and laid the timing analysis across that." In addition to emulation, two complementary ap

30、proaches to design verification are simulation and model checking, a type of formal verification. Simulation applies vectors to a software model of a design and checks to sec if the output has the correct value. The approach is straightforward, but is becoming increasingly tortuous as designs become

31、 more complicated and the number of possible test vectors mushrooms. So recently, electronic design automation companies have been turning to model checking to prove that designs are correctly done. The sticking point with model checking is its great difficulty of use. "It is not for most engin

32、eers," said Simon Napper, chief operating officer OF Innol-ogic Systems Inc., San Jose, Calif. "The usage model is very difficult-it checks properties. But the designer isn't familiar with what P property is-he is used to simulation and static timing." As a remedy, InnoLogic devel

33、oped a symbolic simulation tool, which blends simulation and formal verification. It is a Virology simulator except instead of sending Is and Os through the logic, the too1 propagates symbol or symbols plus binary values.The user gains improved functional coverage dong with much faster verification.

34、 To illustrate, to completely verify a fourbit adder would require 256 binary vectors-and take 256 simulation cycles. With symbols, it takes just one cycle.Just as with formal verification, there are limits to the complexity of the circuits that symbolic simulation can completely verily. Both have t

35、rouble with multipliers, for example. "A model checker will grind and grind and never produce a result," explained Napper. "But in our tool we take some symbol inputs and switch them to binary values, that reduces the job from a 32- to a 16-bit multiplier. And we report to the user th

36、at we were able to verify the upper the operands." InnoLogic has announced two Versifies of symbolic simulation. ESI'-XV verifies designs written in Virology. EXP-CV is meant for custom designs and memory blocks. THE TIME IS RIGHT Though the design of ICs with semiconductor geometries below

37、 0.25 pm face challenges throughout development, some of the biggest hurdles occur during physical design, when the gates are placed on the chip and the interconnects are routed between them Problems occur here for a number of reasons. First, the capacitance, resistance, and inductance of the interc

38、onnects cannot be ignored, as they were in older, larger technologies. Crosstalk between interconnects; now closer together, must also be controlled. Several iterations through synthesis and placement may be necessary to achieve the required timing, if it can be accomplished at all. The solution pro

39、posed by Monterey Design Systems Inc., Sunnyvale, Calif., is called global design technology. This proprietary computing approach simultaneously explores, analyzes, and optimizes all aspects of the physical design. The tint product containing the technology is Dolphin, which was announced in April o

40、f last year. Dolphin simultaneously places and router each gate and flip-flop using the results or the analysis and maintaining all specified constraints. (Most place- and-route tools sequentially analyze the layout for each type of constraint.) It performs timing and logic optimization for every pl

41、acement move.Timing closure is top priority for developers of the Blast Fusion physical design system from Magma Design Automations., Cupertino, Calif. Its methodology, called FixedTiming, brings timing within specified limits without iterating between synthesis and physical design .Basically, he ap

42、proach fixes timing first, then adjusts cell sizes to achieve the timing requirements. Varying the cell sizes always he tool to supply the right drive strength or the load.EDA ON THE WEB As established electronic design automation companies try to sort out how to utilize the internet in their produc

43、t Inks, smaller, more agile companies and start-ups arc coining up with innovative products and services, mainly in the areas or design management. A pioneer in this area is Synchronicity Inc., a virtual company headquartered in Marlboro, Mass. Synchronicity is now being joined by other companies se

44、eking to use the internet to advantage. The concern of CCAES.COM, Milpitas, Calif a provider of Web-based engineering tools 'for; design automation, is the extraction of useful information about ICs, chip sets, and boards from suppliers' Web sites. The issue, according to Michael Bitzko, pre

45、sident of the company, is that designers of products based on there components need to be able to obtain information about them quickly and route it to their engineering, manufacturing, and procurement departments as quickly as possible. "In a nutshell,” said Bitzko, "people used to take w

46、eeks to get data sheets. Then along cane the Web and PDF-formatted documents. But in order to create, ray, schematic symbols and footprints fur printed circuit boards, information from PDF documents must often be reentered-a costly and time-consuming process when time to infarct is a concern. CCAES.

47、COM's products are based on the electronic component interchange (ECIX) standard developed by EDA standards organization SI, Austin, Texas, and on the Extensible Markup Language (XML), that allows the creation or Web-bask documents having (more functionality than with the conventional Hypertext

48、Markup Language (HTM1.). The companys products include QuickData Server, a parametric search engine for electronic component information, and Quickdata Miner, which transform information contained in PDF data sheets into a usable form. The mission or Genedax Inc., Portland, Ore. is to use the Web to

49、 increase designed ability to create and manage large, complex designs, to iron design ICLISC, and to improve access to intellectual property. The company plans to announce a product in the first quarter or the year. John Ott, vice president of sales and marketing, told Sprctmni that its products wi

50、ll be based on the operating systems and browsers developed by Microsott Corp., Redmond, Wash. Also, the company supports a collaborative Web site, that shows what the technology can do. The site includes a search engine based on AltaVista technology that searches the Web sites of companies related

51、to design auto illation. Ott elaborated, "We also have a free Internet locator server that lets people use Netmeeting a Microsoft product for remote sharing of computer desktops and a Web board where you can post questions and get answers." Other aspects of electronic design on the Webs ha

52、ve been slower in taking off than design and information management. But Transim Corp also bared in Portland, Ore, has taken a big step toward Web-based design tools. Its product, Websim, is an interface between a Web browser and Simples, the companys power-supply simulator. Websim allows designers,

53、 using Simplis, to simulate designs over the Internet. So rather than poring over data sheets and looking at ranges of values, designers can see actual waveforms, explained Ncls Gahbert, Transim president and chief executive officer.Transim is working with suppliers to set up component models so tha

54、t designers can log on to the supplies Web rite, select parts for their power supply, enter setup or test conditions, and run the simulation on line. Users need nothing more than a Web browser. The simulation is run on Transim's "ranch" of six strivers from Sun Microsystems. The compan

55、y has teamed up with National Semiconductor Corp, Santa Clara, Calif., to provide this service for National's customers. The cost is on a per-use basis and is a minimal US $10. 附錄C 翻譯中文電子設計自動化關鍵字 電子設計自動化； 集成電路； VHDL語言；現場可編程門陣列在這個片上系統開始出現的時候，有三個問題一直困擾著集成電路設計者。首先就是缺乏一些東西即設計的硬件部件與軟件部件之間缺少統一的語言。這樣由于

56、每一個芯片的邏輯閘門的數量超過了百萬，因此，對設計正確性的驗證瞬間比設計本身更加艱巨。另外，不僅僅是閘門數量問題，集成芯片的頻率也在加大。因此，為了滿足時間需要，做出一個不用反復設計的設計是遙遠的目標。 由于已長期研究電子設計自動化，對于這方面的關注經常受到一些新建的公司抨擊。那些公司是由幾個志向遠大啟動資金缺乏的人領導。您說superlog？芯片系統由電路和軟件組成運行。這樣的系統一般包含一個嵌入的處理器核運行軟件調制解調器。通常，芯片的功能被寫在紙上后，硬件部件就交給了集成電路設計者，軟件部件就給了程序設計者，在以后的某個閘門在合起來組在一起。芯片的一部分功能在邏輯閘門核晶體管被寫入硬件描

57、述語言-verilog語言或VHDL語言時結束。而另外一部分功能將在軟件被描述在編程語言C或C+中結束。這種不同語言的使用給描述，仿制，調試集成電路的線路和軟件的條理清晰方面都帶來了很大的不便。 從工業角度上看我們相信是時候推出一種新的設計語言處理硬件和軟件的問題，使系統從最初的設計規格直達最后的檢驗。加利福尼亞州的協同設計自動化公司的san jose發展了這種新型語言。在成立這個蒸蒸日上的企業前，合作者，現經營主任simon davidmann和peter flake已經得出了為滿足片上系統發展現有語言的實用性。選為被發展的現有語言有C,C+,Java和Verilog。davidmann說一

58、種設計語言必須滿足三個需求。第一應該連接設計過程。第二應該使設計更為高效。第三應該由一種現存的方法演變而來。沒有一種現存的方法滿足這些需求，于是davidmann和flake決定發明一種新的協同設計語言，并命名為superlog。davidmann解釋說“一個很自然的基準點就是連接verilog語言和C語言，從算法觀點上來看，大多數verilog語言都是建立在C語言基礎上的。”這時用比特和VHDL語言與Java語言將其連接起來。從Verilog andVHDL方面，superlog獲得了設計中描述硬件方面的能力，例如順序邏輯，組合邏輯和多值邏輯。從C和Java方面superlog又集成了動態處

59、理器和其他軟件編制。甚至像接口程序，活動網絡路由協議和狀態機等現階段仍常被寫在紙上的功能也能被新的語言描述了。為了處理已經存在的硬件描述或編程語言的遺留問題，superlog允許verilog語言和C語言模塊輸入并允許其直接使用。davidmann說這門語言推廣到公共領域使用是非常重要的。公司已經開始和不同標準的組織合作工作達到其推廣的目的。不被忽視是建立在語言上的設計工具套裝軟件的需要，目前協同設計公司已經和一些電子設計自動化公司確立了合作關系。其中magma 設計自動化公司，sente公司和viewlogic公司將發展建立的superlog上的工具。協同設計公司將繼續為設計程序的前景開發新的產品。沖向終點的比賽并不是每一個人都相信我們需要新的語言。SystemC語言，一個建模平臺，擴展了C/C+的容量和優勢到硬件領域，已經被推薦為一個可選擇的方案。許多像synopsys公司，coware公司，lucent技術公司和德州器具公司等大型權威的公司已經在開放性system C下聯結在一起，開始創立他們下一代設計平臺的版本。為了使system C重新運行，這個組提供了一個建模平臺在他們的網址里免費下載。他們也希望他們的平臺能成為實際的標準。據synopsys公司總