六十秒倒計時一、分化設計要求二、設計計劃路線三、軟件設計四、調試五、實現一、分化設計要求1、實現數碼管連續顯示數字2、實現在數碼管上顯示組合003、在數碼管上逆序顯示00至59這60種組合4、實現60種組合每秒鐘按相應數字顯示5、由于硬件要求是數碼管所有相同段并聯，所以要求利用計數分時掃描的方法二、設計計劃路線1、采用層次性設計中自頂向下混合設計。釋義：所謂自頂向下的設計方法，是指設計電子系統先從系統最抽象的層次出發，作高層次仿真，經過仿真驗證后再經整體規劃(FloorPlanning)將系統行為操作分為多個子系統。由剛才的設計要求可知我們需要譯碼輸出模塊，以顯示數不斷變化的數字，并需要計數器產生60種相對于譯碼器的輸入信號，我們這里采用減計數器模塊，計數器需要1Hz脈沖，所以要有3MHz轉1Hz的分頻器計數分時掃描模塊由于以下硬件電路的接法，所以采用計數分時，即用計數器的不同計數區段來區分每一顯示位的顯示，要求每位顯示時間小于24分之1秒，這樣在視覺上可以達到組數碼管同時顯示不同的數；（利用視覺暫留）3、軟件設計LIBRARYieee;USEieee.std_logic_1164.all;useieee.std_logic_unsigned.all;--EntityDeclarationENTITYcounter60IS --{{ALTERA_IO_BEGIN}}DONOTREMOVETHISLINE! PORT ( reset:INSTD_LOGIC; en:INSTD_LOGIC; clk1h:INSTD_LOGIC; q:OUTSTD_LOGIC_VECTOR(5downto0) ); --{{ALTERA_IO_END}}DONOTREMOVETHISLINE!

ENDcounter60;減計數器模塊ARCHITECTUREcounter60_architectureOFcounter60ISsignalq1:STD_LOGIC_VECTOR(5downto0);

BEGINprocess(clk1h,en,reset)beginifen='1'thenif(clk1h'eventandclk1h='1')then

ifq1>0thenq1<=q1-1;elseq1<="111011";endif;endif;

endif;endprocess;q<=q1;ENDcounter60_architecture;LIBRARYieee;USEieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;--EntityDeclarationENTITYfpqIS PORT ( clk3m:INSTD_LOGIC; clk1:OUTSTD_LOGIC );

ENDfpq;ARCHITECTUREfpq_architectureOFfpqIS signalfp1:std_logic; signaltout:integerrange0to30000;signaltout1:integerrange0to100;signaltout2:std_logic;

BEGINprocess(clk3m)beginif(clk3m'eventandclk3m='1')theniftout>=29999thentout<=0;elsetout<=tout+1;endif;iftout<=14999thentout2<='1';elsetout2<='0';endif;endif;endprocess;process(tout2)beginif(tout2'eventandtout2='1')theniftout1>=99thentout1<=0;elsetout1<=tout1+1;endif;iftout1<=49thenfp1<='1';elsefp1<='0';

endif;endif;endprocess;clk1<=fp1;ENDfpq_architecture;分頻器模塊LIBRARYieee;USEieee.std_logic_1164.all;useieee.std_logic_unsigned.all;--EntityDeclarationENTITYjishu1000IS --{{ALTERA_IO_BEGIN}}DONOTREMOVETHISLINE! PORT ( rst:INSTD_LOGIC; clk100m:INSTD_LOGIC; kai:INSTD_LOGIC; s:OUTSTD_LOGIC_VECTOR(9downto0) ); --{{ALTERA_IO_END}}DONOTREMOVETHISLINE!

ENDjishu1000;--ArchitectureBodyARCHITECTUREjishu1000_architectureOFjishu1000IS

signals1:std_logic_vector(9downto0);

BEGINprocess(clk100m,rst,kai)beginifkai='1'then

ifclk100m'eventandclk100m='1'thenifs1<"0100000000"thens1<=s1+1;elses1<="0000000000";endif;endif;endif;endprocess;s<=s1;ENDjishu1000_architecture;加計數器LIBRARYieee;USEieee.std_logic_1164.all;useieee.std_logic_unsigned.all;ENTITYyimaIS PORT ( i:INSTD_LOGIC_VECTOR(5downto0); de:OUTSTD_LOGIC_VECTOR(6downto0); rj:outSTD_LOGIC; rj60:outstd_logic; jishu100:inSTD_LOGIC_VECTOR(9downto0);

dig:OUTSTD_LOGIC_VECTOR(1downto0) );

ENDyima;ARCHITECTUREyima_architectureOFyimaISsignalrj1:STD_LOGIC;signalr:std_logic;beginprocess(i,jishu100)begincaseiiswhen"111011"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")then

de<="0010000";dig<="10";--9endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;when"111010"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="0000000";dig<="10";--8endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;when"111001"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="1111000";dig<="10";--7endif;

when"110111"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="0010010";dig<="10";--5endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;

when"110110"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="0011001";dig<="10";--4endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5

endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;when"111000"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="0000010";dig<="10";--6endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;

when"110101"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="0110000";dig<="10";--3endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;when"110100"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")then