FPGA技術(shù)課程作業(yè)FPGA技術(shù)課程作業(yè)FPGA技術(shù)課程作業(yè)FPGA技術(shù)課程作業(yè)編制僅供參考審核批準(zhǔn)生效日期地址：電話：傳真:郵編:1.分析程序,完成下列各題：1）完成程序填空。2）畫(huà)出該代碼綜合后的電路圖。moduletest2(clk,reset,in1,in2,in3,out1,out2);inputclk,reset;inputin1,in2,in3;outputout1,out2;regout1,out2;integertemp1,temp2;always@(posedgeclkorposedgereset)if(reset) begin temp1<=0; temp2<=0; end elsebegin temp1<=in1&in2; temp2<=in2|in3; end always@(posedgeclk) begin out1<=temp1&temp2; out2<=temp1^in3; endendmodule2、分析程序，完成下列題目：1）完成程序填空。2）根據(jù)圖一所畫(huà)出的輸入激勵(lì)波形，編寫(xiě)測(cè)試文件，仿真截圖在0到900ns時(shí)間區(qū)間里輸出端口的輸出波形。moduletest1(data_1,data_2,data_3,data_out1,data_out2);inputdata_1,data_2,data_3;outputdata_out1,data_out2;taskwriteburst;inputa,b;integerc;c=a+b;endtaskregdata_out1,data_out2;always@(data_1ordata_2or3)beginwrite(data_1,data_2,data_out1);write(data_2,data_3,data_out2); endendmodule圖一3.根據(jù)下面的VerilogHDL代碼，畫(huà)出綜合后的電路圖。moduletest12(out,clk,in1,in2,in3,in4);inputclk;inputin1,in2,in3,in4;outputout;regout;regtemp1,temp2;always@(posedgeclk)begintemp1<=in1&in2;temp2<=temp1|in3;out<=temp2|in4;endendmodule4.根據(jù)圖1所示的原理圖寫(xiě)出相應(yīng)的VerilogHDL程序，其中DFF模塊是上升沿觸發(fā)的觸發(fā)器，編寫(xiě)相應(yīng)的測(cè)試程序，在ISE軟件中完成仿真，對(duì)仿真波形圖進(jìn)行截圖。圖二程序：

modulemy_moduke(clk,xin,out);inputclk,xin;outputout;regout;regtemp;always@(posedgeclk)begintemp<=xin|out;endalways@(posedgeclk)beginout=temp;endendmodule激勵(lì)文件：initial begin clk=0; forever#30clk=~clk; endinitialbegin 用VerilogHDL設(shè)計(jì)一個(gè)四分頻電路，在ISE軟件中完成仿真，對(duì)仿真波形圖進(jìn)行截圖。1）輸入信號(hào)：clk--------輸入時(shí)鐘reset--------同步復(fù)位信號(hào)，當(dāng)reset=1’b1時(shí)，系統(tǒng)輸出置零，當(dāng)reset=1’b0時(shí)，系統(tǒng)正常工作。2）輸出信號(hào)：clk_out--------輸出信號(hào)，其頻率是輸入時(shí)鐘的四分之一moduleD_4div(clkin,reset_n,clkout);inputclkin,reset_n;outputclkout;wirein1,in2,clkin_2;regout;regclkout_1;assignin1=~clkout_1;assignclkin_2=clkout_1;assignin2=~out;assignclkout=out;always@(posedgeclkin)計(jì)一個(gè)帶有異步復(fù)位控制端和時(shí)鐘使能控制端的10進(jìn)制計(jì)數(shù)器。module

Counter(clk,clk_key,clr,ena,cout,sel,seg);input

clk,clk_key,clr,ena;output

cout;output

[7:0]sel,seg;assign

sel=8'hf0;wire

clk_k;debounce_module

U0

(.CLK(clk),.RSTn(clr),.Pin_In(clk_key),.Pin_Out(clk_k));wire

[3:0]sum;count

U1(.clk(clk),.clk_k(clk_k),.clr(clr),.ena(ena),.cout(cout),.sum(sum));tube

U2(.clk(clk),.sum(sum),.seg(seg));endmodule計(jì)數(shù)模塊module

count(clk,clk_k,clr,ena,cout,sum);input

clk,clk_k,clr,ena;output

cout;output

[3:0]sum;reg

cout;reg

[3:0]sum;reg

a,b;always@(posedge

clk)begina<=clk_k；b<=a;endwire

key_posedge=(~b&a)

1'b1

:1'b0;always@(posedge

clk)beginif(clr)begincout

<=0；sum

<=0;endelse

if(key_posedge

&

ena) beginif(sum<4'd9) beginsum<=sum+1'b1;cout<=0;endelse

begincout<=1; sum<=0;endendelsebegincout<=cout；sum<=sum;endendendmodule數(shù)碼管moduletube(clk,sum,seg);inputclk;input[3:0]sum;output[7:0]seg;reg[7:0]seg;always@(posedgeclk)begincase(sum) 4'd0:seg<=8'hc0;4'd1:seg<=8'hf9;4'd2:seg<=8'ha4;4'd3:seg<=8'hb0; 4'd4:seg<=8'h99;4'd5:seg<=8'h92;