其他CMOSSP0829SP0A1886-10-2012第1章SP0827與SP0829協同工作模 SP0827連接SP0829輸出各個模 SP0827連接SP0829輸出展訊SPI模 SP0827連接SP0829輸出展訊2bit模 SP0827連接SP0829輸出MTKSPI模 SP0827時鐘配置說 SP0827連接SP0829時鐘配置說 第2章SP0827與SP0A18協同工 SP0A18及SP0827輸出展訊SPI模 SP0A18及SP0827輸出展訊2bit模 SP0A18及SP0827輸出展訊4bit模 SP0A18及SP0827輸出MTKSPI模 第3章SP0827與SP0A19協同工 SP0827連接SP0A19輸出各個模 SP0827+SP0A19聯合使用有兩種使用方 SP0827+SP0A19聯合使用并口輸出寄存器配置 SP0827+SP0A19時鐘說 第4章版本歷 第1章SP0827SP0829，SP0829SPI_data1/vsyncSPI_data_inSPI_clk接到SP0829的SPI_DATA[2]，SPI_DATA[1]輸出vsync,，SPI_DATA[0]輸出vsyncSPI_data_inSPI_data_ouSPI_clk_ouwrite(8'h2e,8SPIwrite(8'h2c//pclk接到SP0829的SPI_DATA[2]，SP0829SPI_DATA[1]輸出SPI_data[1SPI_DATA[0]輸出SPI_data[0]信號,PCLK輸出SPI_clkSPI_data0SPI_data1SPI_data_inECLK//pclk接到SP0829的SPI_DATA[2]，SPI_DATA[0]輸出SPI_data[0]信號,PCLK輸出SPI_clkMTK（見下表）SPI_data_inSPI//pclkclk[7][6:4]PCLK000—001010011100101[3:1]ISPclocksettingfrom000001010011100101110111[0][7]Fixframe[6]Upside[5][4]PCLK0x30只能有以下幾種配置6M，PCLK輸出48MrawSPI.3M，PCLK輸出24MrawSPI.M，輸出12MrawSPI.75M，PCLK6M，6Mraw0829PCLK1/20829PCLK工作的時候08290829的前兩種模式配置時鐘。第2章SP0827SP0A18PadPad--SPI_dataDATA_PAD[0（SP0827寄存器2,15MSP0827寄存器2,15MRAWSPI，30MYUVSPI//pclk//輸出不分頻,24MRAWSPI，或者輸入//輸出不分頻,24MRAWSPI，或者輸入，48MYUVSPI//pclkwrite(8'h2e,8，DATA_PAD[1]（，PCLK（連接到展訊6610平臺對應的接收端。SP0827寄存器//15MRAWSP0827寄存器//15MRAWwrite(8'h1b,8//pclk，DATA_PAD[1]（，DATA_PAD[2]（，DATA_PAD[3]（，PCLK（別連接到展訊6610平臺對應的接收端。//15MRAW//15MRAWwrite(8'h1c,8//7.5MYUVccir6564bitwite(8'h31,8'h00);pclkw，PCLK（SPI_clk）MTK6252平臺對應的接收端。SP0827寄存器,15MRAWSP0827寄存器,15MRAWSPISP0A18寄存器，30MYUV//pclkSP0827寄存器//輸出不分頻,24MRAWSPI，或者輸48M，write(8'h30,8'h1824MRAWSP0827寄存器//輸出不分頻,24MRAWSPI，或者輸48M，write(8'h30,8'h1824MRAWSP0A18寄存器，48MYUVSPI//pclk第3章SP0827SP0A19PadPadPCLKSPI_DATSP0827pwda.08270x1c0x03;0x250x03SP0827SPI_clk,SPI_datpad從而使SP0A19pwd拉低。SP0827pwdSP0A19p0~0x2ea.0827pwdb.SP08270x1c0x03;0x250x03,SP0827SPI_clk,SPI_datSP0A19pwd拉低.（SP0827模擬電路）.SP0827pwdGPIOSP0A19pwdGPIOSP0827得SPI_DAT管腳相連：A）當可以控制外部斷電時，直接對SP0827SP0A19直接斷電即SP0827pwdSP0A19p0~0x2eSP0A19pwdSP0827寄存器SP0827寄存器write(8'h25,8'h03);（SP0827SPI_datSP0A19：write(8'hfd,8'h00);write(8'h1c,8'h00);（打開SP0A19pad）write(8'h2e,8'h01);(打開SP0A19輸入使能)write(8'h32,8'h08);AE,SP0827寄存器：write(8'h1c,8'h00);（打開SP0827pad）SP0827寄存器SP0827寄存器write(8'h25,8h03);（SP0827SP0A19：write(8'hfd,8'h00);write(8'h1c,8'h00);（打開SP0A19pad）write(8'h2e,8'h01);(打開SP0A19輸入使能)write(8'h32,8'h08);AE,write(8'hfd,8'h00);(page0)write(8'h2e,8'h01SP0A19pwdwrite(8'h30,8'h02);（SP0A19clk4dclkpclkwrite(8'h32,8'h08);(關閉AEwrite(8'h1c,8'h00)（SP08