1FPGA示器用來顯示允許通行或通行的時間倒計時。本設計我們是基于FPGA的采用大規模可編程邏輯器件FPGA，通過設計來實現譯碼顯示模塊6六部分組成。本設計在XilinxISE和 SE軟件平臺上使用VHDL語2顯示的順序為：左轉 綠 黃 紅燈15秒、80秒、45秒、5秒。狀態表如表所表3- 紅紅紅紅綠黃55紅綠黃紅紅紅6六部分組成。各個模塊的關系與構架如下圖所示。1S的脈沖波。程序如下libraryuseuseieee.std_logic_unsigned.all;entityfenpinqi port(clk1khz:inclk1hz:outstd_logic); architectureaoffenpinqiisprocess(clk1khz) q:integer:=0; ifclk1khz'eventandclk1khz='1'thenifq=512thenr:=notr; elseendif;endif;endprocess;enda;controlcontrolclkSS的值來決定紅綠燈的狀程序如下libraryuseuseieee.std_logic_unsigned.all;entitycontrolisport(clk:ins:outstd_logic_vector(2downto0);loadat,loadbt:outstd_logic;at,bt:outstd_logic_vector(6downto0)); architectureaofcontrolsignalt:integerrange0to130:=0; clk'eventandclk='1'then then elsift=15then elsift=60thenelsift=65then elsift=80 s<="100";elsift=125 endendift=130then endif;endprocess;endclk，就進行一次減一操作。atdaojishi模塊程序libraryuseuseieee.std_logic_unsigned.all;entityatdaojishiisport(clk,loadat:in std_logic_vector(6downto0); std_logic_vector(6downto0));endarchitectureaofatdaojishisignalcountat:std_logic_vector(6downto0);waituntilifloadat='1' elsecountat<=countat-1;endif;endprocess;endMainlibraryuseuseieee.std_logic_unsigned.all;entitymainisport s:instd_logic_vector(2downtolrgy:outstd_logic_vector(7downtoendarchitectureaofmainisvariableb:std_logic_vector(7downto0);caseswhen=>when=>when=>when=>when=>when => whenothers=>b:=" endcase;endprocess;end譯碼程序如下libraryuseuseieee.std_logic_unsigned.all;entityto8421bcdisport( std_logic_vector(3downto0); std_logic_vector(6downto0));endarchitectureaofto8421bcdis ifat>=" "then " " " " " " "endif;ifbt>=" "then " " " " " " "endif;endprocess;enda;libraryuseuseieee.std_logic_unsigned.all;entityyimaxianshiisport(at1,bt1:instd_logic_vector(3downto0);at2,bt2:instd_logic_vector(6downto0);aout1,aout2,bout1,bout2:outstd_logic_vector(7downto0));endyimaxianshi;architectureaofyimaxianshiiscaseat1when"0000"=> when"0001"=> when"0010"=> when"0011"=> when"0100"=> when"0101"=> when"0110"=> when"0111"=> when"1000"=> when"1001"=> others=>aout1<=" endcase;case when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>"; others=>aout2<=" endcase;case when"0000"=> when"0001"=> when"0010"=> when"0011"=> when"0100"=> when"0101"=> when"0110"=> when"0111"=> when"1000"=> when"1001"=> others=>bout1<=" endcase;casebt2when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>"; others=>bout2<=" endcase;endprocess;enda;模塊、yima模塊和yimaxianshi模塊。這些模塊均經過設計、編譯、仿真，結果正確。最后 測試和效果評估在分頻器程序仿真結果圖中，clk1khz1khz；clk1hz為輸出脈1hz的信號。controlloadat，loadbtdaojishi模塊測試（含兩個clk，執行一次，并將結果輸出。Mainmain模塊程序仿真結果圖中，S為輸入信號，用來表明整個紅綠燈的狀態（6個狀態：S0~S5）;lrgy為輸出信號，代表整個紅綠燈的亮和滅的情況，燈的排序從到低綠燈、黃燈，然后南北方向左轉燈、紅燈、綠燈、黃燈。從圖中我們可以看出S的狀態從”到“101aout1代表十位，aout2代表個位；bout1，bout2bt的值分解成個位和十bout1代表十位，bout2代表個位。仿真結果完全正確，符合預期。**Failure:(vsim-3807)Typesdonotmatchbetweencomponentandentityforport Time:0 tion: Instance:/abc_abc_sch_tb/uut/xlxi_2File:control.vhd#**Failure:(vsim-3807)Typesdonotmatchbetweencomponentandentityforport Time:0 tion: Instance:/abc_abc_sch_tb/uut/xlxi_2File:control.vhd#**Failure:(vsim-3807)Typesdonotmatchbetweencomponentandentityforport Time:0 tion: Instance:/abc_abc_sch_tb/uut/xlxi_2File:control.vhd 幻燈片文JPEG[1].