微機原理與接術小組項目報TeamProjectTinyALU<團隊成員：、、組長：082602082597082652082713 1ALU是處理器(CPU)的執行單元，是所有處理器的組成部分。它的基本操TinyALU的設計方法和理念是：使用現場可編程邏輯門陣列（FiledProgrbleGateArray,FPGA）和硬件描述語言（Very-highSpeedIntegratedCircuitHardwareDescriptionLanguage,VHDL）ALU。它具有多種指令，實現了算數的累加，減法以及移位測試的功能，最后采用VHDL語言中的語句對其進試。ISEsymbol出現總是輸出無效信號情況，因此，我們所有的元件都是根據整個系統自己編寫設計（schvhd等文件，并testbanch2TinyALU完成算數加減和移位測試的功能，支持標志寄存器和累計器8根數據線，8RESET等必須的控制信號線。TinyALUFPGA的引腳ALUVHDLFPGATinyALU來實現FPGA的TinyALU在速度上的進一步優化。3圖一TinyALUTinyALU0做運算，隨后控制輸出端的寄存器給加減法器送另一個數據，這樣FPGA將一位全加器設計為一個一位加減器，這樣能使整體結構變得更加簡單。Adder8模塊。對應加減法器模塊。Latch模塊。對應鎖存器模塊。Shifter模塊。對應位移器模塊。Do_flag4圖二完整tinyALU注：圖中除了輸入輸出以外貼的只是為了對整個系統進行調試數據用的模塊一位加減法器（add1cinM——模式選擇（m=0時做加法，m=1時做減法Ifcs=1thenIfm=1thensum=xxoryxorcincout=(xandy)or(xandcin)or(yandcin);sum=xxoryxorcout=(notxandy)or(notxandcin)or(xand(noty)andcin);圖圖鎖存器（LATCH）模塊:鎖存器原件圖如圖四所示。鎖存器的原理比較簡單，在本項目中設計為當CS上升沿到來時，輸入并在下一個上升沿到來前保持該輸出。位移器（Shifter）模塊：8csCLK外，a,b兩個輸入來選擇位移器的模式。X0-x7y0-y7為輸出管腳。a=0,b=0時，位移器向右平移，并補充零。a=0,b=1a=1,b=011001100If（a=0and If(a=0and If(a=1andb=0) If(a=1andb=1)

m08位數相加后產生了進位就說明有益mcout的或運算結果輸出就為溢出位。cout（1為負，0為正）c=mandcout;b=(notm)andcout;end

圖六標志 110000110000010000001111000011000101FBSHRROR一、ALUa0—圖中黃線處為加法器啟動后第9個脈沖到來時刻，因此DO為： 二、ALU減能在第一個脈沖先送入了一 ，然后再第二個脈沖送 ，輸出DO為比如最后黃線處，a5,a61,1， （TXT文本中，以_tb結尾的為測試文件USEIEEE.STD_LOGIC_TEXTIO.ALL;USESTD.TEXTIO.ALL;entityadd1port( : :in :in :in :in cout:out :out endarchitectureBEHAVIORALofadd1isifcs='1'thenifm='1'sum<=xxoryxorcinafter1cout<=(xandy)or(xandcin)or(yandcin)after1ns;sum<=xxoryxorcinafter1cout<=(notxandy)or(notxandcin)or(xand(noty)andcin)after1ns;endif;endendprocess;USEieee.std_logic_1164.ALL;USEieee.numeric_std.ALL;useuseIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_TEXTIO.ALL;USESTD.TEXTIO.ALL;entityshifterport(a:inb:inclk:incs:inx0:inx1:inx2:inx3:inx4:inx5:inx6:inx7:instd_logic;y0:outstd_logic;y1:outstd_logic;y2:outstd_logic;y3:outstd_logic;y4:outstd_logic;y5:outstd_logic;y6:outstd_logic;y7:outendarchitectureBEHAVIORALofshifterisprocessifcs='1'if(rising_edge(clk))ifa='0'andb='0'then --linearrightelsifa='0'andb='1'then --linearleftelsifa='1'andb='0'then--circlerightelsifa='1'andb='1'then--circleleftendif;endif;endif;endprocess;endlibraryuseIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_TEXTIO.ALL;USESTD.TEXTIO.ALL;entitydo_flagport(cout: : : :out enddo_flag;architectureBEHAVIORALofdo_flagisc<=mandcout;b<=(notm)andcout;end VHDLLIBRARYUSEieee.std_logic_1164.ALL;USEieee.numeric_std.ALL;useUSEIEEE.STD_LOGIC_TEXTIO.ALL;USEentityalubport( : a1:instd_logic;a2:instd_logic;a3:instd_logic;a4:instd_logic;a5:instd_logic;a6:instd_logic;clk:instd_logic;di0:in : : : : : : : reset: : :outstd_logic;do0:outstd_logic;do1:outstd_logic;do2:outstd_logic;do3:outstd_logic;do4:outstd_logic;do5:outstd_logic;do6:outstd_logic;do7:outstd_logic;i0:outstd_logic;i1:outi2:outi3:outi4:outi5:outi6:outi7:outstd_logic;o0:outstd_logic;o1:outstd_logic;o2:outstd_logic;o3:outstd_logic;o4:outstd_logic;o5:outstd_logic;o6:outstd_logic;o7:outstd_logic;o10:outstd_logic;o11:out::::::::::::::endarchitectureBEHAVIORALofalubissignalXLXN_112 :std_logic;signals0_DUMMY :std_logic;signals1_DUMMY :std_logic;signals2_DUMMY :std_logic;signals3_DUMMY :std_logic;signals4_DUMMY :std_logic;signals5_DUMMY :std_logic;signals6_DUMMY :std_logic;signals7_DUMMY :std_logic;signalo10_DUMMY:std_logic;signalo11_DUMMY:std_logic;signalo12_DUMMY:std_logic;signalo13_DUMMY:std_logic;signalo14_DUMMY:std_logic;signalo15_DUMMY:std_logic;signalo16_DUMMY:std_logic;signalo17_DUMMY:std_logic;signali0_DUMMY :std_logic;signali1_DUMMY :std_logic;signali2_DUMMY :std_logic;signali3_DUMMY :std_logic;signali4_DUMMY :std_logic;signali5_DUMMY :std_logic;signalo0_DUMMY :std_logic;signali6_DUMMY :std_logic;signalo1_DUMMY :std_logic;signali7_DUMMY :std_logic;signalo2_DUMMY:std_logic;signalo3_DUMMY:std_logic;signalo4_DUMMY:std_logic;signalo5_DUMMY:std_logic;signalo6_DUMMY:std_logic;signalo7_DUMMY:std_logic;componentlatch2port(clk:in : reset:in :in :in :in :in :in :in :in :in :out :out :out :out :out :out :out :outstd_logic);endcomponentport(:::::::::::::::::::::::::::coutendcomponent:a:b::a:b:::::::::::::::::endcomponent;componentport(m:instd_logic;cout:instd_logic;c:outb:outstd_logic);endcomponent;componentport(x0: y0: x1: y1: x2: y2: x3: y3: x4: y4: x5: y5: x6: y6: x7: y7:instd_logic;q0:outstd_logic;q1:outstd_logic;q2:outstd_logic;q3:outstd_logic;q4:outstd_logic;q5:outstd_logic;q6:outstd_logic;q7:outendi0<=i0_DUMMY;i1<=i1_DUMMY;i2<=i2_DUMMY;i3<=i3_DUMMY;i4<=i4_DUMMY;i5<=i5_DUMMY;i6<=i6_DUMMY;i7<=o0<=o0_DUMMY;o1<=o1_DUMMY;o2<=o2_DUMMY;o3<=o3_DUMMY;o4<=o4_DUMMY;o5<=o5_DUMMY;o6<=o7<=o7_DUMMY;o10<=o10_DUMMY;o11<=o11_DUMMY;o12<=o12_DUMMY;o13<=o13_DUMMY;o14<=o14_DUMMY;o15<=o15_DUMMY;o16<=o16_DUMMY;o17<=o17_DUMMY;s0<=s0_DUMMY;s1<=s1_DUMMY;s2<=s2_DUMMY;s3<=s3_DUMMY;s4<=s4_DUMMY;s5<=s5_DUMMY;s6<=s6_DUMMY;s7<=XLXI_1:portmapXLXI_2:portmapXLXI_3:portmapXLXI_4:portmapXLXI_6:portmapXLXI_7:portmapendALULIBRARYUSEieee.std_logic_1164.ALL;USEieee.numeric_std.ALL;useUSEIEEE.STD_LOGIC_TEXTIO.ALL;USEENTITYalub_alub_sch_tbISENDalub_alub_sch_tb;ARCHITECTUREbehavioralOFalub_alub_sch_tbCOMPONENTPORT(i0:OUTSTD_LOGIC;i1:OUTSTD_LOGIC;i3:OUTSTD_LOGIC;i4:OUTSTD_LOGIC;i5:OUTSTD_LOGIC;i6:OUTSTD_LOGIC;i7:OUTo0:OUTSTD_LOGIC;o7:OUTSTD_LOGIC;o10:OUTSTD_LOGIC;o11:OUTSTD_LOGIC;o12:OUTSTD_LOGIC;o13:OUTSTD_LOGIC;o14:OUTSTD_LOGIC;o15:OUTSTD_LOGIC;o16:OUTSTD_LOGIC;o17:OUT OUTOUTOUTOUTOUTOUTOUTOUTcbi2OUTOUTOUTOUTOUTOUT:::::::::::::::::::::::ENDSIGNALi0: SIGNALi1: SIGNALi3: SIGNALi4: SIGNALi5: SIGNALi6: SIGNALi7: SIGNALo0: SIGNALo7: SIGNALo10 SIGNALo11 SIGNALo12 SIGNALo13 SIGNALo14 SIGNALo15 SIGNALo16 SIGNALo17 SIGNALdi0: SIGNALdi1: SIGNALdi2: SIGNALdi3: SIGNALdi4: SIGNALdi5: SIGNALdi6: SIGNALdi7:STD_LOGIC;SIGNALreset:STD_LOGIC;SIGNALa0:STD_LOGIC;SIGNALa1:STD_LOGIC;SIGNALclk:STD_LOGIC;SIGNALa2:STD_LOGIC;SIGNALa3:STD_LOGIC;SIGNALa5:STD_LOGIC;SIGNALa6:STD_LOGIC;SIGNALdo0:STD_LOGIC;SIGNALdo1:STD_LOGIC;SIGNALdo2:STD_LOGIC;SIGNALdo3:STD_LOGIC;SIGNALdo4:STD_LOGIC;SIGNALdo5:STD_LOGIC;SIGNALdo6:STD_LOGIC;SIGNALdo7:STD_LOGIC;SIGNALc:STD_LOGIC;SIGNALb:STD_LOGIC;SIGNALi2:STD_LOGIC;SIGNALo1:STD_LOGIC;SIGNALo2:STD_LOGIC;SIGNALo3:STD_LOGIC;SIGNALo4:STD_LOGIC;SIGNALo5:STD_LOGIC;SIGNALo6:STD_LOGIC;SIGNALs0:STD_LOGIC;SIGNALs1:STD_LOGIC;SIGNALs2:STD_LOGIC;SIGNALs3:STD_LOGIC;SIGNALs4:STD_LOGIC;SIGNALs5:STD_LOGIC;SIGNALs6:STD_LOGIC;SIGNALs7:STD_LOGIC;SIGNALa4:UUT:alubPORTMAP(i0=>i0,i1