集成電路分析與設計第1講認識集成電路設計及其設計過程2023/2/61《集成電路分析與設計》課程主要介紹什么內容?CMOS數字集成電路(CMOSdigitalIC)IC的發展歷史及現狀(HistoryofIC)IC設計流程和方法(DesignprocessandMethodology)IC制造工藝技術(Fabricationprocess)ICEDA（CAD）工具使用(EDAtools)CMOS反相器設計(CMOSInverter)CMOS組合邏輯門設計(CombinationalLogicCircuit)CMOS時序邏輯電路設計(SequentialLogicCircuit)IC版圖設計(Layout)IC仿真技術(Simulation)存儲器電路設計介紹(MemoryCircuits)模擬IC設計介紹(AnalogIC)2023/2/62《集成電路分析與設計》課程信息課程性質：是一門專業基礎課程主要介紹CMOS數字集成電路設計的基礎知識共40課時（32理論課時+8實驗課時）完成4個實驗對準備從事IC行業的學生來講，本課程只是一個基礎，還需要繼續深入學習更多關于IC設計的知識，如數字IC深入，模擬IC，RFIC等。2023/2/63Project（選作內容）完成一個44SRAM芯片的設計3人一組項目過程：A期中OralpresentationB期末OralpresentationC項目報告書一份D3人項目成績相同2023/2/65GradingPolicy課堂提問和作業10%實驗20%考試（開卷）70%規則：（1）1個問題和4次作業，每次/個2分，共10分；（2）每個實驗完成得5分，共20分；（3）點名1次不到，10分沒了；（4）抄作業，抄實驗報告，相應分數沒了；（5）請假規則：必須有正規請假手續和課前請假。2023/2/66

本課程推薦書目

教材中文版周潤德等譯，數字集成電路設計透視第二版，電子工業出版社(JanM.Rabaey,etal.DigitalIntegratedCircuits,2nde,PrenticeHall,2004)參考書Sung-Mo(Steve)Kang,YusufLeblebici,CMOSDigitalIntegratedCircuitsAnalysis&Design,3rdEdition,McGraw-Hill2003R.JacobBaker,CMOSCircuitDesign,Layout,andsimulation,3rdEdition,Wiley,2010韓雁，集成電路設計CAD/EDA工具實用教程，機械工業出版社，20102023/2/67幾個常見縮略詞CMOS(complementarymetaloxidesemiconductor)IC(integratedcircuit)VLSI(verylargescaleintegrated)ULSI(ultra-largescaleintegrated)MOSFET(metaloxidesemiconductorfieldeffecttransistors)SPICE(simulationprogramwithintegratedcircuitemphasis)2023/2/69認識集成電路和集成電路設計為什么需要集成電路？與以前的集成電路設計相比，為什么現在的集成電路設計出現了不同以及現在的集成電路設計遇到了哪些新的挑戰？未來，集成電路將如何發展？2023/2/610為什么需要集成電路?Integrationreducesdevicesize（減小尺寸）Laptop,iPod,mp3,cellphone,...Integrationimprovesthedesign（提高性能）higherspeed;lowerpowerconsuption;morereliable.Integrationreducesmanufacturingcost（降低成本）BOM(BoardofMaterials)costreducesMassICproductionreducescost2023/2/611Moore’sLaw(1965)GordonMoore–IntelFounder“Thenumberoftransistorsonachipdoubledevery18to24months.”Electronics,April19,1965.GordonMooreIntelCo-FounderandChairmainEmeritusImagesource:IntelCorporation2023/2/613InformationRevolutionElectronicsystemincars.Electronicfinancialsystem:e-banking,e-money,e-stock,RFIDlablePersonalcomputing/entertainmentMedicalelectronicsystems.Internet:routers,firewalls,servers,storagesElectroniclibrary(Google,...)DVDR/W,HDTV,InteractiveTVIngeneral,consumerelectronicsetc...2023/2/614ChallengesofICDesignComplexity:Multi-milliontransistorsonasinglechip(smallersize/fasterspeed)Multipleandconflictingspecificationsforhighperformance(power/speed/throughput)Competition:ShortdesigntimeDesignTools:Multipletoolsinvolved,ComplexdesignflowAnalogBasebandDigitalBaseband(DSP+MCU)PowerManagementSmallSignalRFPowerRF2023/2/6152023/2/617TheTransistorRevolutionFirsttransistorBellLabs,1947J.Bardeen,W.Shockley,andW.Brattain(1956NobelprizeLaureate)2023/2/6181958年J.Kilby（TI）研制成功第一個集成電路1959年R.Noyce（Fairchild）第一個利用平面工藝制成集成電路TheFirstIntegratedCircuits2023/2/619

Intel4004Micro-Processor19702300transistors~1MHzoperation2023/2/621IntelPentium(IV)microprocessorPentium?4“Northwood”CommercialProduction:Year2001L=0.13μm6MLCuLow-kFC-PGA22023/2/622MOSFETTechnologyMOSFETtransistor-Lilienfeld(Canada)in1925andHeil(England)in1935CMOS–1960’s,butplaguedwithmanufacturingproblems(usedinwatchesduetotheirpowerlimitations)PMOSin1960’s(calculators)NMOSin1970’s(4004,8080)–forspeedCMOSin1980’s–preferredMOSFETtechnologybecauseofpowerbenefitsBiCMOS,Gallium-Arsenide,Silicon-GermaniumSOI,Copper-LowK,strainedsilicon,High-kgateoxide...2023/2/6231’’Waferin1964vs.300mm(12”)Waferin20032023/2/625IBMPowerPC970(130nm)20031.8Ghz58M118mm2ApplePowerG5,thefastestPCin2003,hasdualPPC970CPU2023/2/626TwochipsyouareseeingtodayMicroprocessorASIC(ApplicationSpecificIC)2023/2/627State-of-theArt:LeadMicroprocessors(uptodate)

Pentium4180nm(2001)1.7GHz42Mtransistors217mm2Pentium4130nm(2003)3.2GHz55MTransistors131mm2Pentium490nm(2004)3.4Hz125MTransistors112mm2Pentiumon65nm(2005/2006)250Million

Pentiumon45nm(2007)400to500Million(Alluse0.13umtechnologyexceptPentium4–Prescott,whichuses90nmtech)2023/2/629State-of-theArt:LeadMicroprocessors(uptodate)300mmwaferandPentium4IC.PhotoscourtesyofIntel.2023/2/630WhatADigitalDesignerNeedstoKnow...

“MicroscopicProblems”?Ultra-highspeeddesignInterconnect?Noise,Crosstalk?Reliability,Manufacturability?PowerDissipation?Clockdistribution.

“MacroscopicIssues”?Time-to-Market?MillionsofGates?High-LevelAbstractions?Reuse&IPAvailability?systemsonachip(SoC)

?Predictability?etc.2023/2/6312023/2/6322023/2/6332023/2/6342023/2/6352023/2/6362023/2/6372023/2/638>95%2023/2/639如何設計一個集成電路？2023/2/6402023/2/641TheVLSIdesignprocess工程的藝術Maybepartoflargerproductdesign.Majorlevelsofabstraction:specificationarchitecturelogicdesigncircuitdesignlayoutdesign2023/2/642MajorSegmentsofICIndustryFablessDesignHousesEDAToolsCompaniesDesignServiceCompaniesLibrary&IPProvidersDedicatedICManufacturers(Foundry)Post:EDA:ElectronicDesignAutomationIP:siliconIntellectualPropertyIDM:IntegratedDeviceManufacturerIntegratedservicePackaging&TestingHouses2023/2/643ASICDesignStylesFullCustomDesignFlowCircuitiscreatedbycomposingatransistornetlistSPICEsimulationisperformedtoverifythecircuitKnownas“capture-and-simulate”paradigmLayoutismostlydonemanuallyPopularforhigh-performancemicroprocessors&memoriesCell-BasedSynthesisFlowDesignisfirstdescribedbyHardwareDescriptionLanguage(e.g.,VerilogandVHDL)Basedonacelllibrary,netlistiscreatedbysynthesistoolsKnownas“describe-and-synthesize”paradigmLayoutcanbedonethroughautomatictools2023/2/644DetailedCustomDesignFlowBlockSpecification(FiniteStateMachine,ArithmeticExpression,BooleanExpression)LogicDesignGate-LevelNetlistTransistorNetlistTechnologyMappingSPICESimulationSPICEModelLayoutDesignLayoutLayoutRulesDesignRuleChecking(DRC)Layoutvs.SchematicCheck(LVS)Parasitic(orwiring)RCextractionPost-LayoutSPICESimulationCheckifSPECismet?Ifyes,done.Otherwise,gobacktooptimizethedesign2023/2/645ASimpleExample FunctionalityOne-bitbinaryfull-adderTechnology1mmn-wellCMOStechnologySpeedInputtooutputdelay<5nsArea<3000mm2PowerDissipation<1mWat5voltsand200MHzFull-adderABSumCarry_outSum=A⊕B⊕C=ABC+ABC+ABC+ACBCarry_out=AB+BC+CA(majorityfunction)BooleanDescriptionC2023/2/646LogicDesignLogicminimizationtrick:Thecarry_outsignalisusedtorealizethefunctionofsignalsum

inordertoreducetheoverallcircuitsize.Today’slogicsynthesistools(suchasDesignCompiler)incorporatingsomeadvancedalgorithms,isabletoperformautomaticlogicminimization.x=Carry_out#of‘1’sInA,B,C

Carry_out

Sum012300110101(A+B+C)x=>exactlyoneofA,B,Cis‘1’2023/2/647Transistor-LevelSchematicTechnologymappingManysimpleANDORgatesaremergedintoacomplexgate(oracellinthecelllibrary)TransistoraspectratiopMOS(W/L)isusuallylargerthannMOS(W/L),e.g.,2:1xyxyx=(AB+BC+CA)y=(A+B+C)x+ABC)2023/2/648InitialLayoutPost-layoutSPICEsimulationincludesthe“parasiticresistance&capacitance”ismoreaccuratethanthepre-layoutsimulation(pre-sim)Ratioofchannelwidths2:12023/2/649I/OSimulationWaveformsPropagationtimetPHLortPLHasdefinedaboveLow-to-highpropagationtime（傳播延時）tPLH=8.2ns!

Gottogobacktooptimizethedesign!!!C(Carry_in)Sum2023/2/650OptimizedLayoutTransistorSizingchangestheaspectratios

(W/L)ofselectedtransistorsAlargeraspectratiomayleadtoahigherspeedWireSizingisalsomorerecentlyproposedPropagationDelay<5ns!2023/2/651FullCustomDesignExample（another)A/DPLAI/OcompRAMMetal1ViaMetal2I/OPadRandomlogic(standardcelldesign)2023/2/652Cell-BasedDesignFlowArchitecturedesignSystem-levelintegrationlayoutNoviolationMemorymoduleFunctionalmodelTestbenchRTLcoding&simulationRTLcodeCellLibrarysynthesisviewRTL-synthesis(DesignCompiler)NetlistphysicalviewPlace&Route(Apollo)LayoutviolationPost-LayoutTimingCheck(DesignTime)SDFSDF:standarddelayformat2