1、Sequential Logic Test1.1 INTRODUCTION The previous chapter examined methods for creating sensitized paths in combina- tional logic extending from stuck-at faults on logic gates to observable outputs. We now attempt to create tests for sequential circuits where the outputs are a function not just of

2、present inputs but of past inputs as well. The objective will be the same: to create a sensitized path from the point where a fault occurs to an observable out- put. However, there are new factors that must be taken into consideration. A sensi- tized path must now be propagated not only through logi

3、c operators, but also through an entirely new dimensiontime. The time dimension may be discrete, as in synchronous logic, or it may be continuous, as in asynchronous logic. The time dimension was ignored when creating tests for faults in combinational logic.It was implicitlyassu med that the output

4、response would stabilize before being measured with test equipment, and it was generally assumed that each test pat- tern was independent of its predecessors. As will be seen, the effects of time cannot be ignored, because this added dimension greatly inuences the results of test pat- tern generatio

5、n and can complicate, by orders of magnitude, the problem of creating tests. Assumptions about circuit behavior must be carefully analyzed to determine the circumstances under which they prevail. 1.2 TEST PROBLEMS CAUSED BY SEQUENTIAL LOGIC Two factors complicate the task of creating tests for seque

6、ntial logic: memory and circuit delay. In sequential circuits the signals must not only be logically correct, but must also occur in the correct time sequence relative to other signals. The test prob- lem is further complicated by the fact that aberrant behavior can occur in sequential circuits when

7、 individual discrete components are all fault-free and conform to their manufacturers specications. We rst consider problems caused by the presence of memory, and then we examine the effects of circuit delay on the test generation problem.1.2.1 The Effects of Memory In the rst chapter it was pointed

8、 out that, for combinational circuits, it was possible (but not necessarily reasonable) to create a complete test for logic faults by applying all possible binary combinations to the inputs of a circuit. That, as we shall see, is not true for circuits with memory. They may not only require more than

9、 2 tests, but are also sensitive to the order in which stimuli are applied. Test Vector Ordering The effects of memory can be seen from analysis of the cross-coupled NAND latch cf. Figure 2.3(b). Four faults will be considered, these being the input SA1 faults on each of the two NAND gates (numberin

10、g is from top to bottom in the diagram). All four possible binary combinations are applied to the inputs in ascending orderthat is, in the sequence (Set, Reset) = (0,0), (0,1), (1,0), (1,1). We get the following response for the fault-free circuit (FF) and the circuit corresponding to each of the fo

11、ur input SA1 faults. Input Output Set Reset FF 1 2 3 40 0 1 0 1 1 10 1 1 0 1 1 11 0 0 0 0 0 11 1 0 0 0 1 1In this table, fault number 2 responds to the sequence of input vectors with an output response that exactly matches the fault-free circuit response. Clearly, this sequence of inputs will not di

12、stinguish between the fault-free circuit and a circuit with input 2 SA1.The sequence is now applied in the exact opposite order. We get:Input OutputSet Reset FF 1 2 3 41 1 ? ? 0 1 ?1 0 0 0 0 0 ?0 1 1 0 1 1 10 0 1 0 1 1 1The Indeterminate Value When the four input combinations are applied in reverse

13、order, question marks appear in some table positions. What is their signi- cance? To answer this question, we take note of a situation that did not exist when dealing only with combinational logic; the cross-coupled NAND latch has memory. By virtue of feedback present in the circuit, it is able to r

14、emember the value of a sig- nal that was applied to the set input even after that signal is removed. Because of the feedback, neither the Set nor the Reset line need be held low any longer than necessary to effectively latch the circuit. However, when power is rst applied to the circuit, it is not k

15、nown what value is contained in the latch. How can circuit behavior be simulated when it is not known what value is contained in its memory? In real circuits, memory elements such as latches and ip-ops have indetermi- nate values when power is rst applied. The contents of these elements remain indet

16、erminate until the latch or ip-op is either set or reset to a known value. In a simulation model this condition is imitated by initializing circuit elements to the indeterminate X state. Then, as seen in Chapter 2, some signal values can drive a logic element to a known state despite the presence of

17、 indeterminate values on other inputs. For example, the AND gate in Figure 2.1(c) responds with a 0 when any single input receives a 0, regardless of what values are present on other inputs. However, if a 1 is applied while all other inputs are at X, the output remains at X. Returning to the latch,

18、the rst sequence began by applying 0s to both inputs, while the second sequence began by applying 1s to both inputs. In both cases the internal nets were initially indeterminate. The 0s in the rst sequence were able to drive the latch to a known state, making it possible to immediately distinguishbe

19、tween correct and incorrect response. When applying the patterns in reverse order, it took longer to drive the latch into a state where good circuit response could be dis- tinguished from faulty circuit response. As a result, only one of the four faults is detected, namely, fault 1. Circuits with fa

20、ults 2 and 3 agree with the good circuit response in all instances where the good circuit has a known response. On the rst pattern the good circuit respons is indeterminate and the circuit with fault 2 responds with a 0. The circuit with fault 3 responds with a 1. Since it is not known what value to

21、 expect from the good circuit, there is no way to decide whether the faulted circuits are responding correctly. Faulted circuit 4 presents an additional complication. Its response is indetermi- nate for both the rst and second patterns. However, because the good circuit has a known response to patte

22、rn 2, we do know what to look for in the good circuit, namely, the value 0. Therefore, if a NAND latch is being tested with the second set of stimuli, and it is faulted with input 4 SA1, it might come up initially with a 0 on its output when power is applied to the circuit, in which case the faul is

23、 not detected, or it could come up with a 1, in which case the fault will be detected. Oscillations Another complication resulting from the presence of memory is oscillations. Suppose that we rst apply the test vector (0,0) to the cross-coupled NAND latch. Both NAND gates respond with a logic 1 on t

24、heir outputs. We then apply the combination (1,1) to the inputs. Now there are 1s on both inputs to each of the two NAND gatesbut not for long. The NAND gates transform these 1s into 0s on the outputs. The 0s then show up on the NAND inputs and cause the NAND out- puts to go to 1s. The cycle is repe

25、titive; the latch is oscillating. We do not know what value to expect on the NAND gate outputs; the latch may continue to oscillate until a different stimulus is applied to the inputs or the oscillations may eventually subsideIf the oscillations do subside, there is no practical way to predict, from

26、 a logic description of the circuit, the nal state into which the latch settles. Therefore, the NAND outputs are set to the indeterminate X. Probable Detected Faults When we analyzed the effectivenes of binary sequences applied to the NAND latch in descending order, we could not claim with certainty

27、 that stuck-at fault number 4 would be detected. Fortunately, that fault is detected when the vectors are applied in ascending order. In other circuits the ambi- guity remains. In Figure 2.4(b) the Data input is complemented and both true and complement values are applied to the latch. Barring the p

28、resence of a fault, the latch will not oscillate. However, when attempting to create a test for the circuit, we encounter another problem. If the Enable signal is SA1, the output of the inverter driven by Enable is permanently at 0 and the NAND gates driven by the inverter are permanently in a 1 sta

29、te; hence the faulted latch cannot be initialized to a known state. Indeterminate states were set on the latch nodes prior to the start of test pattern generation and the states remain indeterminate for the faulted circuit. If power is applied to the fault-free and faulted latches, the circuits may

30、just happen to come up in the same state. The problem just described is inherent in any nite-state machine (FSM). The FSM is characterized by a set of states Q = q , q , ., q , a set of input stimuli 1 2 s I = i , i , ., i , another set Y = y , y , ., y of output responses, and a pair of 1 2 n 1 2 m

31、 Mappings M : Q I Q Z : Q I Y These mappings dene the next state transition and the output behavior in response to any particular input stimulus. These mappings assume knowledge of the current state of the FSM at the time the stimulus is applied. When the initial stimulus is applied, that state is u

32、nknown unless some independent means such as a reset exists for driving the FSM into a known state. In general, if there is no independent means for initializing an FSM, and if the Clock or Enable input is faulty, then it is not possible to apply just a single stimu- lus to the FSM and detect the pr

33、esence of that fault. One approach used in industry is to mark a fault as a probable detect if the fault-free circuit drives an output pin to a known logic state and the fault causes that same pin to assume an unknown state. The industry is not in complete agreement concerning the classication of pr

34、oba- ble detected faults. While some test engineers maintain that such a fault is likely to eventually become detected, others argue that it should remain classied as undetec- ted, and still others prefer to view it as a probable detect. If the probable detected fault is marked as detected, then the

35、re is a concern that an ATPG may be designed to ignore the fault and not try to create a test for it in those situations where a test exists.The Initialization Problem Consider the circuit of Figure 5.1. During simula- tion, circuit operation begins with the D ip-op in an unknown state. In normal op

36、eration, when the input combination A = B = C = 0 is applied and the ip-op is clocked, the Q output switches to 0. The ip-op can then be clocked a second time to obtain a test for the lower input of gate 3 SA1. If it is SA1, the expected value is Q = 1; and if it is fault-free, the expected value is

37、 Q = 0. Unfortunately, the test has a serious aw! If the lower input to gate 3 is SA1, the output of the ip-op at the end of the rst clock period is indeterminate because the value at the middle input to gate 3 is initially indeterminate. It is driven by the ip- op that has an indeterminate value. A

38、fter a second clock pulse the value at Q will remain at X; hence it may agree with the good circuit response despite the presence of the fault. The fallacy lies in assuming correct circuit behavior when setting up the ip-op for the test. We depended upon correct behavior of the very net that we are

39、attempting to test when setting up a test to detect a fault on that net. To correctly establish a test, it is necessary to assume an indeterminate value from the ip-op. Then, from the D-algorithm, we know that the ip-op must be driven into the 0 state, without depending on the input to gate 3 that i

40、s driven by the ip- op. The ip-op value can then be used in conjunction with the inputs to test for the SA1 on the lower input of gate 3. In this instance, we can set A = C = 0, B = 1. Then a 1 can be clocked into the ip-op from gate 2. This produces a 0 on the out- put of the ip-op which can then b

41、e used with the assignment A = B = 0 to clock a 0 into the ip-op. Now, with Q = 0 and A = B = C = 0, another clock causes D to appear on the output of the ip-op. Notice that input C was used, but it was used to set up gate 2. If input C were faulted in such a way as to affect both gates 2 and 3, the

42、n it could not have been used to set up the test.1.2 .2 Timing ConsiderationsUntil now we have assumed that erroneous behavior on circuit outputs was the result of logic faults. Those faults generall result from actual physical defects such as opens or shorts, or incorrect fabrication such as an inc

43、orrect connection or a wrong component. Unfortunately, this assumption, while convenient, is an oversimplica- tion. An error may indeed be a result of one or more logic faults, but it may also be the case that an error occurs and none of the above situations exists. Defects exist that can prevent an

44、 element from behaving in accordance with its specications. Faults that affect the performance of a circuit are referred to as para- metric faults, in contrast to the logic faults that have been considered up to this point. Parametric faults can affect voltage and current levels, and they can affect

45、 gain and switching speed of a circuit. Parametric faults in components can result from improper fabrication or from degradation as a consequence of a normal aging process. Environmental conditions such as temperature extremes, humidity, or mechanical vibration can accelerate the degradation process

46、. Design oversights canproduce symptoms similar to parametric faults. Design problems include failure to take into account wire lengths, loading of devices, inad- equate decoupling, and failure to consider worst-case conditions such as maximum or minimum voltages or temperatures over which a device

47、may be required to oper- ate. It is possible that none of these factors may cause an error in a particular design in a well-controlled environment, and yet any of these factors can destabilize a cir- cuit that is operating under adverse conditions. Relative timing between signal paths or the ability

48、 of the circuit to drive other circuits could be affected.Intermit tenterrors are particularly insidious because of their rather elusive nature, appearing only under particular combinations of circumstances. For exam- ple, a logic board may be designed for nominal signal delay for each component as

49、a safety margin. Statistically, the delays should seldom accumulate so as to exceed a critical threshold. However, as with any statistical expectation, there will occasion- ally be a circuit that does exceed the maximum permissible value. Worse still, it may work well at nominal voltages and /or tem

50、peratures and fail only when voltages and/ or temperatures stray from their nominal value. A new board substituted for the orig-inal board may be closer to tolerance and work well under the degraded voltage and or temperature conditions. The original board may then, when checked at a depot or a boar

51、d tester under ideal operating conditions, test satisfactorily. Consider the effects of timing variations on the delay ip-op of Figure 2.7. Cor- rect operation of the ip-op requires that the designer observe minimal setup and hold times. If propagation delay along a signal path to the Data input of

52、the ip-op is greater than estimated by the designer, or if parametric faults exist, then the setup time requirement relative to the clock may not be satised, so the clock attempts to latch the signal while it is still changing. Problems can also occur if a signal arrives too soon. The hold time requ

53、irement will be violated if a new signal value arrives at the data input before the intended value is latched up in the ip-op. This can hap- pen if one register directly feeds another without any intervening logic.That logic or parametric faults can cause erroneous operation in a circuit is easy to

54、understand, but digital test problems are further compounded by the fact that errors can occur during operation of a device when it components behave as intended. Elements used in the fabrication of digital logic circuits contain delay. Ironically, although technologists constantly try to create fas

55、ter circuits and reduce delay, sequential logic circuits cannot function without delay; circuits depend both on correct logic operation of circuit components and on correct relative timing of signals passing through the circuit. This delay must be taken into account when designing and testing circui

56、ts. Suppose the inverter driven by the Data input in the gated latch circuit of Figure 2.4(b) has a delay of n nanoseconds. If the Data input makes a 0-to-1 transi- tion followed by a 0-to-1 transition on the Enable approximately n nanoseconds later, the two cross-coupled NAND gates see an input of

57、(0,0) for about n nanosec- onds followed by an input of (1,1). This produces unpredictable results, as we have seen before. The problem is caused by the delay in the inverter. A solution to this problem is to put a buffer in the noninverting signal path so the Data and Data sig- nals reach the NANDs

58、 at about the same time. In each of the two circuits just cited, the delay ip-op and the latch, a race exists. A race is a condition wherein two or more signals are changing simulta- neously in a circuit. The race may be caused by multiple simultaneous input signal changes, or it may be the result o

59、f a single signal change that follows two or more paths from a fanout point. Note that any time we have a latch or ip-op we have a race condition, since these devices will always have at least one element whose sig- nal both goes outside the device and feeds back to an input of the latch or ip-op. R

60、aces may or may not affect the behavior of a circuit. A critical race exists if the behavior of a circuit depends on the outcome of the race. Such races can produce unanticipated and unwanted results. Hazards can also cause sequential circuits to behave in ways that were not intended. In Section 2.6